Patent application number | Description | Published |
20080266207 | Display Device and Related Driving Method Using Low Capacity Row Buffer Memory - In a method for driving a display device, an address counter is used for generating a plurality of address variables corresponding to data of a scan line. Next, an address mapping circuit generates a first target address by data-mapping an address variable, and generates a second target address by data mapping data stored in an address look-up table memory. Subsequently, a row buffer memory accesses data corresponding to a first scan line based on the first target address, and accesses data corresponding to a second scan line based on the second target address. | 10-30-2008 |
20110205793 | METHOD FOR ACCESSING MULTI-LEVEL NON-VOLATILE MEMORY CELL - A method for accessing a multi-level non-volatile memory cell includes the following steps: determining at least one target word line voltage according to a target bit to be read from a plurality of bits stored in the multi-level non-volatile memory cell; and applying the at least one target word line voltage to the multi-level non-volatile memory cell in order to determine the target bit. Herein the at least one target word line voltage includes at most 2 | 08-25-2011 |
20130013895 | BYTE-ORIENTED MICROCONTROLLER HAVING WIDER PROGRAM MEMORY BUS SUPPORTING MACRO INSTRUCTION EXECUTION, ACCESSING RETURN ADDRESS IN ONE CLOCK CYCLE, STORAGE ACCESSING OPERATION VIA POINTER COMBINATION, AND INCREASED POINTER ADJUSTMENT AMOUNT - An exemplary byte-oriented microcontroller includes a program memory, a program memory bus, and a core circuit. The program memory bus has a bus width wider than one instruction byte, and the core circuit is coupled to the program memory through the program memory bus for executing at least one instruction by processing a plurality of instruction bytes fetched from the program memory. The core circuit includes a fetch unit, for fetching the instruction bytes through the program memory bus and re-ordering the fetched instruction bytes to form a complete instruction. | 01-10-2013 |
Patent application number | Description | Published |
20090174613 | ARRAY ANTENNA AND ELECTRONIC APPARATUS USING THE SAME - An array antenna and an electronic apparatus using the array antenna are provided. The array antenna includes a plurality of antenna units, a first connection line, and a second connection line. Each of the antenna units includes a rectangular radiation region, a first feeding line and a second feeding line. The first and second feeding lines are connected to two adjacent feeding corners of the rectangular radiation region. The first connection line and the second connection line are disposed at two sides of the antenna unit for connection with the other ends of the first feeding line and the second feeding line, respectively. | 07-09-2009 |
20100134377 | PLANAR ANTENNA - A planar antenna including a substrate, multiple antenna bodies and a metal layer is provided. The antenna bodies are disposed at a surface of the substrate, and the metal layer is disposed at another surface of the substrate. The metal layer has multiple slots which interlace with the antenna bodies. The antenna bodies are partially corresponding to the metal layer and used to cooperate with a communication system which can perform a multi-path transmission to send and receive electromagnetic signals for a multiple MIMO system simultaneously. | 06-03-2010 |
20120194391 | MIMO ANTENNA SYSTEM - A multi-input multi-output (MIMO) antenna system includes multiple antennas, a ground part and an isolating part. The isolating part is disposed between each two adjacent antennas. The isolating part is electrically connected to the ground part. A distance exists between an end of the antenna and an end of the isolating part. A circuit board applying the MIMO antenna system is also disclosed. Since the isolating part is disposed between each two adjacent antennas, signal interference between the antennas can be prevented, and the MIMO antenna system and the circuit board applying the same have better isolation. | 08-02-2012 |
20130120207 | ANTENNA MODULE - An antenna module includes a substrate, a casing and at least two antennas. The substrate is disposed in the casing, and the antennas are disposed on the substrate and perpendicular to each other. Accordingly, the entire size of the antenna module can be decreased and it is still possible to provide the optimum signal transmission performance. | 05-16-2013 |
Patent application number | Description | Published |
20140040846 | CROSSTALK ANALYSIS METHOD - An embodiment of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; generating a layout suggestion when the crosstalk value is larger than the predetermined value. | 02-06-2014 |
20140250415 | CROSSTALK ANALYSIS METHOD - One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value. | 09-04-2014 |
20140317585 | CROSSTALK ANALYSIS METHOD - An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing an interface for showing information of the layout result and adjusting a plurality of lines of the layout circuit. | 10-23-2014 |
20150286767 | CIRCUIT LAYOUT METHOD AND CIRCUIT LAYOUT APPARATUS - A circuit layout method and a circuit layout apparatus are disclosed. The circuit layout apparatus comprises a display apparatus, an input device, a stack up database and a processor. The display apparatus shows a system interface. The input device inputs a user request in response to the system interface. The processor selects a stack up data table, corresponding to the user request, from the stack up database, and generates a design rule of a computer aided design (CAD) according to the stack up data table. The processor checks whether a circuit board design complies with the design rule. | 10-08-2015 |