Patent application number | Description | Published |
20100118617 | MEMORIES WITH IMPROVED WRITE CURRENT - A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level. | 05-13-2010 |
20100153043 | MONITORING METHOD FOR THROUGH-SILICON VIAS OF THREE-DIMENSIONAL INTERGRATED CIRCUIT (3D IC) AND APPARATUS USING THE SAME - A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal. | 06-17-2010 |
20100237386 | ELECTROSTATIC DISCHARGE STRUCTURE FOR 3-DIMENSIONAL INTEGRATED CIRCUIT THROUGH-SILICON VIA DEVICE - An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device. | 09-23-2010 |
20120249178 | MONITORING METHOD FOR THREE-DIMENSIONAL INTERGRATED CIRCUIT (3D IC) AND APPARATUS USING THE SAME - A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same. | 10-04-2012 |
Patent application number | Description | Published |
20150115461 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The method includes following steps. A first wafer is provided, which includes a first region, a second region, and a first semiconductor device disposed in the first region. No semiconductor device is disposed in the second region. A second wafer is provided, which includes a third region, a fourth region and a second semiconductor device disposed in the third region. No semiconductor device is disposed in the fourth region. The first region of the first wafer is overlapped with the fourth region of the second wafer. The second region of the first wafer is overlapped with the third region of the second wafer. A first conductive through via is formed to pass through the fourth region of the second wafer and the first region of the first wafer to electrically connect to the first semiconductor device. | 04-30-2015 |
20160064295 | TEST KEY ARRAY - The present invention provides a test key array including a lower conductive pattern, and the lower conductive pattern includes a plurality of first L-shaped traces parallel to each other, an upper conductive pattern, where the upper conductive pattern includes a plurality of second L-shaped traces parallel to each other, the lower conductive pattern crosses to the upper conductive pattern, and a plurality of cross regions are defined between the lower conductive pattern and the upper conductive pattern, and a plurality of conductive plugs, disposed on parts of the cross regions, electrically connecting to the lower conductive pattern and the upper conductive pattern. | 03-03-2016 |
Patent application number | Description | Published |
20120000066 | Method for Manufacturing Alloy Resistor - An alloy resistor and a fabrication method thereof are provided. A fabrication method of an alloy resistor includes: providing an alloy sheet having a plurality of openings spacing apart from each other and going through the alloy sheet and a plurality of alloy resistor units located between any two adjacent openings, wherein each of the alloy resistor units has an insulating cover area and a plurality of electrode ends on both sides of the insulating cover area; forming an insulating layer on a surface of the insulating cover area of the alloy resistor units by an electrodeposition coating process; cutting the alloy along a connecting portion, so as to obtain separated alloy resistor units; and forming a conductive adhesion material on the electrode ends of the alloy resistor units. An alloy resistor having an insulating layer with a smooth surface can be obtained by performing an electrodeposition coating process. | 01-05-2012 |
20120001212 | Light-Emitting Diode Packaging Structure and Substrate Therefor - A light-emitting diode (LED) packaging structure and a substrate for the packaging structure are provided. The light-emitting diode packaging structure includes a metal substrate having a first surface and a second surface opposite to the first surface, and the first surface has a concave portion with a sidewall and a bottom, allowing an anode film to be formed on the metal substrate; a plurality of electrically conductive pads formed on the bottom of the concave portion; an optical treatment layer formed on the sidewall of the concave portion; and an LED die mounted on the bottom of the concave portion and electrically connected to the electrically conductive pads. Desired electrical insulating property between any two adjacent electrically conductive pads can be obtained by the anode film formed on the metal substrate, while a good thermal conductivity of the metal substrate is maintained. | 01-05-2012 |
20120211792 | Package Substrate and Method for Forming the Same - A package substrate is disclosed. The package substrate includes a substrate body having a conductive portion, a plurality of insulation portions and two surfaces opposing to each other; and a plurality of bonding layers for heat dissipation formed on the two surfaces of the substrate body, conducted via the conductive portion and separated from one another by the insulation portions. A method for forming the package substrate is also disclosed. | 08-23-2012 |
20120317806 | Method for Forming Package Substrate - A method of making a package substrate includes steps of forming a plurality of trenches on a first surface of a metal plate, placing insulation material in the trenches, removing metal plate material under the second surface of the metal plate, and exposing the insulation material in the trenches from substrate. The resulting substrate body includes a conductive portion made of the metal plate, and an insulation portion made of the insulation material. The bonding layers on the opposite sides of the substrate are conducted by the conductive portion for heat dissipation, and are separated from one another by the insulation portion. | 12-20-2012 |
20130048602 | Method of Manufacturing a Metallized Ceramic Substrate - A method of manufacturing a metallized ceramic substrate includes forming a metal layer on a ceramic substrate, and forming on the metal layer a resist having a first patterned resist opening and a second patterned resist opening for the metal layer to be exposed therefrom. A first width of the first patterned resist opening is greater than the thickness of the metal layer, and a second width of the second patterned resist opening is less than the thickness of the metal layer. A wet-etching process is conducted, to form in the first patterned resist opening a patterned metal layer opening and form in the second patterned resist opening a patterned metal layer dent. Therefore, an internal stress between the metal layer and the ceramic substrate is reduced, and the yield rate and reliability of the metallized ceramic substrate is increased. | 02-28-2013 |
20130082292 | Light Emitting Diode Packaging Structure and Method of Fabricating the Same - A method of fabricating alight emitting diode packaging structure provides a metallized ceramic heat dissipation substrate and a reflector layer, and the metallized ceramic heat dissipation substrate is bonded with the reflector layer through an adhesive. The reflector layer has an opening for a surface of the metallized ceramic heat dissipation substrate to be exposed therefrom. The reflector layer may be formed with ceramic or polymer plastic material, to enhance the refractory property and the reliability of the package structure. In addition, the packaging structure of the present invention may make use of existing packaging machine for subsequent electronic component packaging, without increasing the fabrication cost. | 04-04-2013 |
20130089982 | Method of Fabricating a Substrate Having Conductive Through Holes - A method of fabricating a substrate having a plurality of conductive through holes is disclosed. Release films are formed on opposite sides of a substrate, and a plurality of through holes penetrating the release films and the substrate are formed. A first metal layer is formed on the release films and the sidewall of each of the through holes prior to removing the release films and the first metal layer thereon. A second metal layer is formed on the first metal layer on the sidewalls of the through holes by electroless plating. Compared to the prior art, the method is simpler and cheaper to carry out while the conductive through holes and a surface circuit layer thereof are fabricated separately, thereby avoiding disadvantage of forming a circuit layer on the surface of the substrate too thick. | 04-11-2013 |
20130098867 | Method for Selective Metallization on a Ceramic Substrate - A method of selective metallization on a ceramic substrate includes selectively forming an active brazing material on a predetermined area of a surface of a ceramic substrate, attaching the metal layer to the ceramic substrate with the active brazing material, performing a brazing process on the active brazing material, forming an etching stop layer on the metal layer and performing an etching process, and removing the etching stop layer. The method can be applied to a severe environment, and the conchoidal fracture between the ceramic substrate and the metal layer can also be avoided. The present invention not only simplifies the process but also improves the product yield. | 04-25-2013 |
20140001051 | Method of Electroplating and Depositing Metal | 01-02-2014 |
20140167911 | Resistor Component - A resistor component is provided, including a ceramic bar having a film applied thereon, a protection layer formed on the film in a middle portion of the ceramic bar, an end plating layer formed on the film at two ends of the ceramic bar, an insulation layer formed on the protection layer, and a color coded marking formed on the insulation layer that indicates the resistance of the resistor component. The end plating layer is formed by a barrel plating method and includes copper, tin, nickel and a combination thereof. The resistor component thus has a low cost and is manufactured by a simple process, simultaneously avoids the occurrence of pores or incompletely sealed join that may be caused by the prior method. Therefore the resistor component has high reliability. | 06-19-2014 |
20140170848 | Method of Forming Substrate - A method of forming a substrate is provided, which includes steps of providing a metal plate having a first surface and a second surface; forming a plurality of recesses on the first surface of the metal plate by using laser cutting technique; filling the plurality of recesses with an insulating material; removing a part of the metal plate in a direction of from the second surface to the first surface, so that two ends of the insulating material are exposed, and a substrate body is formed by a conductor portion formed by the remaining part of the metal plate and an insulating portion formed by the insulating material; and forming a circuit layer on a first surface of the substrate body and a circuit layer on a second surface of the substrate body is provided. Thus, the two circuit layers are electrically connected by the conductor portion that also provides a heat dissipation path and are separated by the insulating portion. | 06-19-2014 |
Patent application number | Description | Published |
20110100975 | CARRIER FOR HEATING AND KEEPING WARM - A carrier for heating and keeping warm used for directly carrying food to-be kept warm is provided. The carrier for heating and keeping warm includes a carrier and at least a high melt point-electric heating alloy pattern. The carrier has a first surface and a second surface opposite to the first surface. The food is suitable for being directly placed on the first surface. A material of the second surface is ceramics or glass so that the second surface | 05-05-2011 |
20120111872 | COOKING UTENSIL AND MANUFACTURING METHOD THEREOF - A cooking utensil and a manufacturing method thereof are provided. The cooking utensil includes a cooking body, a first metal-ceramic composite layer having an electromagnetic property and a second metal-ceramic composite layer having a heat conductive property. The cooking body has an external bottom surface. The first metal-ceramic composite layer is disposed on the external bottom surface of the cooking body. The second metal-ceramic composite layer is disposed on the first metal-ceramic composite layer. The cooking utensil is suitable for both an induction cooker and a gas burner. | 05-10-2012 |
20130224392 | METHOD FOR PROVIDING A COATING LAYER WITH PROTECTION AND THERMAL CONDUCTIVITY - A method for providing a coating layer with well protection and thermal conductivity, providing a coating layer material, the coating layer material set on a workpiece to form a coating layer with thickness 160˜500 micrometer. The coating layer is able to avoid wear of the surface of the workpiece, and has well protection and thermal conductivity, to avoid the situation of damage or mechanical property changing occurred due to the temperature of the surface rising caused by the friction. | 08-29-2013 |
20150284833 | COATING LAYER WITH PROTECTION AND THERMAL CONDUCTIVITY - A coating layer with well protection and thermal conductivity has a workpiece; and a coating layer with a thickness ranged between 160˜500 micrometer deposited on the workpiece; | 10-08-2015 |
Patent application number | Description | Published |
20100163897 | FLEXIBLE LIGHT SOURCE DEVICE AND FABRICATION METHOD THEREOF - A flexible light source device including a substrate, a light emitting device, a molding compound, a dielectric layer, and a metal line is provided. The substrate has a first surface, a second surface opposite to the first surface, and a first opening. The light emitting device is disposed on the first surface of the substrate and covers the first opening. The molding compound is located above the first surface and covers the light emitting device. The dielectric layer is disposed on the second surface and covers a sidewall of the first opening. The dielectric layer has a second opening which exposes part of the light emitting device. The metal line is disposed on the dielectric layer, wherein the metal line is electrically connected to the light emitting device via the second opening in the dielectric layer. Additionally, a fabrication method of the flexible light source device is also provided. | 07-01-2010 |
20140291790 | ENCAPSULATION OF BACKSIDE ILLUMINATION PHOTOSENSITIVE DEVICE - An encapsulation of backside illumination photosensitive device including a circuit sub-mount, a backside illumination photosensitive device, a plurality of conductive terminals, and a heat dissipation structure is provided. The backside illumination photosensitive device includes an interconnection layer and a photosensitive device array, wherein the interconnection layer is located on the circuit sub-mount, and between the photosensitive device array and the circuit sub-mount. The conductive terminals are located between the interconnection layer and the circuit sub-mount to electrically connect the interconnection layer and the circuit sub-mount. The heat dissipation structure is located under the interconnection layer, and the heat dissipation structure and the photosensitive device array are respectively located at two opposite sides of the interconnection layer. | 10-02-2014 |
20160043239 | PACKAGE STRUCTURE - Conductive plug structures suitable for stacked semiconductor device package is provided, wherein large contact region between the conductive plug structures and the corresponding pads of devices can be achieved, to reduce electrical impedance. Therefore, package structures such as photosensitive device packages using the conductive plug structures have superior electrical performance and reliability. | 02-11-2016 |