Patent application number | Description | Published |
20130042064 | SYSTEM FOR DYNAMICALLY ADAPTIVE CACHING - The present disclosure is directed to a system for dynamically adaptive caching. The system includes a storage device having a physical capacity for storing data received from a host. The system may also include a control module for receiving data from the host and compressing the data to a compressed data size. Alternatively, the data may also be compressed by the storage device. The control module may be configured for determining an amount of available space on the storage device and also determining a reclaimed space, the reclaimed space being according to a difference between the size of the data received from the host and the compressed data size. The system may also include an interface module for presenting a logical capacity to the host. The logical capacity has a variable size and may include at least a portion of the reclaimed space. | 02-14-2013 |
20130339786 | SMART ACTIVE-ACTIVE HIGH AVAILABILITY DAS SYSTEMS - A high availability DAS system uses a solid state cache to provide near active-active performance in a DAS duster, while retaining the implementation simplicity of active-passive or dual active system. Each node in the duster may include a solid state cache that stores hot I/O in an active-active mode, which allows the data to be read from or written to the underlying dual-active or active/passive DAS RAID system only when access to the “hot Region” cools down or in the case of Cache Miss. The hot I/O data includes hot read data that accumulated dynamically regardless of ownership of the drives where the hot read data is permanently stored. The hot I/O data also includes hot write data that is mirrored across the solid state cache memories to avoid potential dirty write data conflicts and also to provide High Availability in case of server failures. | 12-19-2013 |
20140089545 | LEASED LOCK IN ACTIVE-ACTIVE HIGH AVAILABILITY DAS SYSTEMS - A method and system for IO processing in a storage system is disclosed. In accordance with the present disclosure, a controller may take long term “lease” of a portion (e.g., an LBA range) of a virtual disk of a RAID system and then utilize local locks for IOs directed to the leased portion. The method and system in accordance with the present disclosure eliminates inter-controller communication for the majority of IOs and improves the overall performance for a High Availability Active-Active DAS RAID system. | 03-27-2014 |
20140208005 | System, Method and Computer-Readable Medium for Providing Selective Protection and Endurance Improvements in Flash-Based Cache - A cache controller includes a cache memory distributed across multiple solid-state storage units in which cache line fill operations are applied sequentially in a defined manner and write operations are protected by a RAID-5 (striping plus parity) scheme upon a stripe reaching capacity. The cache store is responsive to data from a storage controller managing a primary data store. The cache store arranges the data differently based on the origin or type of data received at the cache interface. Line fill operations are placed in the cache memory without generating and storing corresponding parity information. When a sufficient number of write operations fill strips that constitute a full stripe are present in cache store, a corresponding parity strip is generated and stored in a strip location designated for storage of the parity information. | 07-24-2014 |
20140208024 | System and Methods for Performing Embedded Full-Stripe Write Operations to a Data Volume With Data Elements Distributed Across Multiple Modules - A data storage system and methods for managing data to be transferred between a host and a data volume distributed across solid state storage modules are disclosed. A storage controller couples the host to the data volume and manages data transfers to and from the logical volume. The storage controller receives a set of parameters that define how an array of blocks and chunks of buffered data will be distributed across solid state storage modules. The storage controller receives and buffers data to be stored and transfers the same when the capacity of the buffered data will fill a set of arranged stripes in the defined array in a single write operation. | 07-24-2014 |
20140223071 | METHOD AND SYSTEM FOR REDUCING WRITE LATENCY IN A DATA STORAGE SYSTEM BY USING A COMMAND-PUSH MODEL - A data storage system is provided that implements a command-push model that reduces latencies. The host system has access to a nonvolatile memory (NVM) device of the memory controller to allow the host system to push commands into a command queue located in the NVM device. The host system completes each IO without the need for intervention from the memory controller, thereby obviating the need for synchronization, or handshaking, between the host system and the memory controller. For write commands, the memory controller does not need to issue a completion interrupt to the host system upon completion of the command because the host system considers the write command completed at the time that the write command is pushed into the queue of the memory controller. The combination of all of these features results in a large reduction in overall latency. | 08-07-2014 |
20140223094 | SELECTIVE RAID PROTECTION FOR CACHE MEMORY - A RAID controller includes a cache memory in which write cache blocks (WCBs) are protected by a RAID-5 (striping plus parity) scheme while read cache blocks (RCBs) are not protected in such a manner. If a received cache block is an RCB, the RAID controller stores it in the cache memory without storing any corresponding parity information. When a sufficient number of WCBs to constitute a full stripe have been received but not yet stored in the cache memory, the RAID controller computes a corresponding parity block and stores the RCBs and parity block in the cache memory as a single stripe. | 08-07-2014 |
20140244902 | FAST READ IN WRITE-BACK CACHED MEMORY - An apparatus having a cache and a circuit is disclosed. The cache includes a plurality of cache lines. The cache is configured to (i) store a plurality of data items in the cache lines and (ii) generate a map that indicates a dirty state or a clean state of each of the cache lines. The cache also has a write-back policy to a memory. The circuit is configured to (i) check a location in the map corresponding to a read address of a read request and (ii) obtain read data directly from the memory by bypassing the cache in response to the location having the clean state. | 08-28-2014 |