Patent application number | Description | Published |
20090296491 | MEMORY HAVING P-TYPE SPLIT GATE MEMORY CELLS AND METHOD OF OPERATION - A memory comprising a plurality of P-channel split-gate memory cells are organized in rows and columns. Each of the plurality of P-channel split-gate memory cells comprises a select gate, a control gate, a source region, a drain region, a channel region, and a charge storage layer comprising nanocrystals. Programming a memory cell of the plurality of P-channel split-gate memory cells comprises injecting electrons from a channel region of the memory cell to the charge storage layer. Erasing the memory cell comprises injecting holes from the channel region to the charge storage region. | 12-03-2009 |
20100240206 | METHOD OF ANNEALING A DIELECTRIC LAYER - A method includes forming a first dielectric layer over a substrate; forming nanoclusters over the first dielectric layer; forming a second dielectric layer over the nanoclusters; annealing the second dielectric layer using nitrous oxide; and after the annealing the second dielectric layer, forming a gate electrode over the second dielectric layer. | 09-23-2010 |
20100244121 | STRESSED SEMICONDUCTOR DEVICE AND METHOD FOR MAKING - A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate. | 09-30-2010 |
20110165749 | METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL - A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer. | 07-07-2011 |
20120261769 | METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL - A semiconductor device comprises a semiconductor substrate and a select gate structure over a first portion of the semiconductor substrate. The select gate structure comprises a sidewall forming a corner with a second portion of the semiconductor substrate and a charge storage stack over an area comprising the second portion of the semiconductor substrate, the sidewall, and the corner. A corner portion of a top surface of the charge storage stack is non-conformal with the corner, and the corner portion of the top surface of the charge storage stack has a radius of curvature measuring approximately one-third of a thickness of the charge storage stack over the second portion of the substrate or greater. A control gate layer is formed over the charge storage stack. A portion of the control gate layer conforms to the corner portion of the top surface of the charge storage stack. | 10-18-2012 |
20140050029 | SPLIT-GATE MEMORY CELLS HAVING SELECT-GATE SIDEWALL METAL SILICIDE REGIONS AND RELATED MANUFACTURING METHODS - Split-gate non-volatile memory (NVM) cells having select-gate sidewall metal silicide regions are disclosed along with related manufacturing methods. Spacer etch processing steps are used to expose sidewall portions of select gates. Metal silicide regions are then formed within these sidewall portions of the select gates. Further, metal silicide regions can also be formed in top portions of the select gates. Further, the select gates can also be formed with one or more notches. By expanding the size of the metal silicide region to include the sidewall portion of the select gate, the select gate wordline (e.g., polysilicon) resistance is reduced for split-gate NVM arrays, the electrical contact to the select gate is improved, and performance of the select-gate NVN cell is improved. | 02-20-2014 |
20140211559 | PROGRAMMING A SPLIT GATE BIT CELL - A method of programming a split gate memory applies voltages differently to the terminals of the selected cells and the deselected cells. For cells being programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, programming is achieved by coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage. For cells not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected but sufficiently low to prevent programming. | 07-31-2014 |
20160049303 | METHOD FOR FORMING A MEMORY STRUCTURE HAVING NANOCRYSTALS - A method of forming a semiconductor structure uses a substrate. A first insulating layer is formed over the substrate. An amorphous silicon layer is formed over the first insulating layer. Heat is applied to the amorphous silicon layer to form a plurality of seed nanocrystals over the first insulating layer. Silicon is epitaxially grown on the plurality of seed nanocrystals to leave resulting nanocrystals. | 02-18-2016 |
Patent application number | Description | Published |
20100096686 | ELECTRONIC DEVICE INCLUDING TRENCHES AND DISCONTINUOUS STORAGE ELEMENTS - An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described. | 04-22-2010 |
20100155824 | NANOCRYSTAL MEMORY WITH DIFFERENTIAL ENERGY BANDS AND METHOD OF FORMATION - A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy. | 06-24-2010 |
20110073936 | NANOCRYSTAL MEMORY WITH DIFFERENTIAL ENERGY BANDS AND METHOD OF FORMATION - A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy. | 03-31-2011 |
20110256705 | METHOD FOR FORMING A SPLIT GATE DEVICE - A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer. | 10-20-2011 |
20120261635 | RESISTIVE RANDOM ACCESS MEMORY (RAM) CELL AND METHOD FOR FORMING - A resistive random access memory cell over a substrate includes a memory stack structure and a sidewall spacer. The memory stack structure is over the substrate and includes a first electrode layer, a second electrode layer, and a metal oxide layer between the first electrode layer and the second electrode layer. The metal oxide layer has a sidewall. The sidewall spacer is adjacent to the sidewall and has a composition including silicon, carbon, and nitrogen. | 10-18-2012 |
20120261636 | RESISTIVE RANDOM ACCESS MEMORY (RAM) CELL AND METHOD FOR FORMING - A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer. | 10-18-2012 |
20130264533 | RERAM DEVICE STRUCTURE - A resistive random access memory (ReRAM) includes a first metal layer having a first metal and a metal-oxide layer on the first metal layer. The metal-oxide layer inlcudes the first metal. The ReRAM further includes a second metal layer over the metal-oxide layer and a first continuous conductive barrier layer in physical contact with sidewalls of the first metal layer and of the metal-oxide layer. | 10-10-2013 |
20130320284 | FIELD FOCUSING FEATURES IN A RERAM CELL - A resistive random access memory (ReRAM) cell, comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and an interface region comprising a plurality of interspersed field focusing features that are not photo-lithographically defined. The interface region is located between the first conductive electrode and the dielectric storage material layer or between the dielectric storage material layer and the second conductive electrode. | 12-05-2013 |
20130320285 | FIELD FOCUSING FEATURES IN A RERAM CELL - A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters ( | 12-05-2013 |
20140003155 | SPLIT GATE PROGRAMMING | 01-02-2014 |
20140036568 | RERAM DEVICE STRUCTURE - A resistive random access memory (ReRAM) device can comprise a first metal layer and a first metal-oxide layer on the first metal layer. The first metal-oxide layer comprises the first metal. A second metal layer can comprise a second metal over and in physical contact with the first metal-oxide layer. A first continuous non-conductive barrier layer can be in physical contact with sidewalls of the first metal layer and sidewalls of the first metal-oxide layer. A second metal-oxide layer can be on the second metal layer. The second metal-oxide layer can comprise the second metal layer. A third metal layer can be over and in physical contact with the second metal-oxide layer. The first and second metal-oxide layers, are further characterized as independent storage mediums. | 02-06-2014 |
20140091380 | Split Gate Flash Cell - In one aspect, a disclosed method of fabricating a split gate memory device includes forming a gate dielectric layer overlying an channel region of a semiconductor substrate and forming an electrically conductive select gate overlying the gate dielectric layer. The method further includes forming a counter doping region in an upper region of the substrate. A proximal boundary of the counter doping region is laterally displaced from a proximal sidewall of the select gate. The method further includes forming a charge storage layer comprising a vertical portion adjacent to the proximal sidewall of the select gate and a lateral portion overlying the counter doping region and forming an electrically conductive control gate adjacent to the vertical portion of the charge storage layer and overlying the horizontal portion of the charge storage layer. | 04-03-2014 |
20140209995 | Non-Volatile Memory Cells Having Carbon Impurities and Related Manufacturing Methods - Non-volatile memory (NVM) cells having carbon impurities are disclosed along with related manufacturing methods. The carbon impurities can be introduced using a variety of techniques, including through epitaxial growth of silicon-carbon (SiC) layers and/or carbon implants. Further, the carbon impurities can be introduced into one or more structures within NVM cells, including source regions, drain regions, gate regions, and/or charge storage layers. For discrete charge storage layers that utilize nanocrystal structures, carbon impurities can be introduced into the nanocrystal charge storage layers. The disclosed embodiments are useful for a variety of NVM cell types including split-gate NVM cells, floating gate NVM cells, discrete charge storage NVM cells, and/or other desired NVM cells. Advantageously, the carbon impurities introduce tensile stress into the cell structures, and this tensile stress helps maintain NVM system performance and data retention even as device geometries are reduced. | 07-31-2014 |
20140239372 | SPLIT GATE NON-VOLATILE MEMORY (NVM) CELL AND METHOD THEREFOR - A split gate memory structure includes a pillar of active region having a first source/drain region disposed at a first end of the pillar, a second source/drain region disposed at a second end of the pillar, opposite the first end, and a channel region between the first and second source/drain regions. The pillar has a major surface extending between first and the second ends which exposes the first source/drain region, the channel region, and the second source/drain region. A select gate is adjacent the first source/drain region and a first portion of the channel region, wherein the select gate encircles the major surface the pillar. A charge storage layer is adjacent the second source/drain region and a second portion of the channel region, wherein the charge storage layer encircles the major surface the pillar. A control gate is adjacent the charge storage layer, wherein the control gate encircles the pillar. | 08-28-2014 |
20140295639 | FIELD FOCUSING FEATURES IN A RERAM CELL - A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters ( | 10-02-2014 |
20140319593 | SCALABLE SPLIT GATE MEMORY CELL ARRAY - A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments. | 10-30-2014 |
20140321213 | BIASING SPLIT GATE MEMORY CELL DURING POWER-OFF MODE - A non-volatile memory (NVM) system has a normal mode, a standby mode and an off mode that uses less power than the standby mode. The NVM system includes an NVM array that includes NVM cells and NVM peripheral circuitry. Each NVM cell includes a control gate. A controller is coupled to the NVM array, applies a voltage to the control gates and power to the peripheral circuitry during the standby mode, and applies an off-mode voltage to the control gates and removes power from the NVM peripheral circuitry during the off mode. | 10-30-2014 |
20150035034 | SPLIT GATE NON-VOLATILE MEMORY CELL - A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension. | 02-05-2015 |
20150054044 | Method to Form a Polysilicon Nanocrystal Thin Film Storage Bitcell within a High K Metal Gate Platform Technology Using a Gate Last Process to Form Transistor Gates - A process integration is disclosed for fabricating non-volatile memory (NVM) cells ( | 02-26-2015 |
20150054049 | INTEGRATED SPLIT GATE NON-VOLATILE MEMORY CELL AND LOGIC STRUCTURE - A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate. | 02-26-2015 |
20150054050 | INTEGRATED SPLIT GATE NON-VOLATILE MEMORY CELL AND LOGIC DEVICE - A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer. | 02-26-2015 |
20150069490 | Methods For Forming Contact Landing Regions In Split-Gate Non-Volatile Memory (NVM) Cell Arrays - Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array. | 03-12-2015 |
20150069524 | Method of Forming Different Voltage Devices with High-K Metal Gate - A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device ( | 03-12-2015 |
20150072489 | NON-VOLATILE MEMORY (NVM) CELL AND HIGH-K AND METAL GATE TRANSISTOR INTEGRATION - A method of making a semiconductor device includes depositing a layer of polysilicon in a non-volatile memory (NVM) region and a logic region of a substrate. The layer of polysilicon is patterned into a gate in the NVM region while the layer of polysilicon remains in the logic region. A memory cell is formed including the gate in the NVM region while the layer of polysilicon remains in the logic region. The layer of polysilicon in the logic region is removed and the substrate is implanted to form a well region in the logic region after the memory cell is formed. A layer of gate material is deposited in the logic region. The layer of gate material is patterned into a logic gate in the logic region. | 03-12-2015 |
20150091079 | NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-FIRST METHODOLOGY - A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate. | 04-02-2015 |
20150179816 | NON-VOLATILE MEMORY (NVM) CELL AND A METHOD OF MAKING - A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate. | 06-25-2015 |
20150236035 | Methods For Forming Contact Landing Regions In Split-Gate Non-Volatile Memory (NVM) Cell Arrays - Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array. | 08-20-2015 |
20150380408 | Method of Forming Different Voltage Devices with High-K Metal Gate - A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device ( | 12-31-2015 |
20160035848 | METHOD OF FORMING SPLIT GATE MEMORY WITH IMPROVED RELIABILITY - A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions. | 02-04-2016 |
20160064082 | SEMICONDUCTOR MEMORY CELL AND DRIVER CIRCUITRY WITH GATE OXIDE FORMED SIMULTANEOUSLY - The present disclosure provides for semiconductor structures and methods for making semiconductor structures. In one embodiment, isolation regions are formed in a substrate, and wells are formed between the isolation regions. The wells include a first low voltage well and a second low voltage well in a logic region of the substrate, and a memory array well in an NVM region of the substrate. A first layer of oxide is formed over the first low voltage well and the memory array well, and a second layer of oxide is formed over the second low voltage well, the second layer being thinner than the first layer. Gates are formed over the wells, including a first gate over the first low voltage well, a second gate over the second low voltage well, and a memory cell gate over the memory array well. Source/drain extension regions are formed around the gates. | 03-03-2016 |
20160071960 | NON-VOLATILE MEMORY (NVM) CELL AND A METHOD OF MAKING - A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate. | 03-10-2016 |
Patent application number | Description | Published |
20090153739 | Method and Apparatus for a Noise Filter for Reducing Noise in a Image or Video - A noise filter method and apparatus for producing at least one of a video or an image with reduced noise. The noise filter method includes performing noise estimation on a frame of at least one of an image or video and applying a low pass filter on the noise level according to the noise estimation, performing spatial filtration on the frame, performing motion detection on a spatially filtered frame, determining motion-to-blending factor conversion and, accordingly, performing frame blending, and outputting a frame with reduced noise. | 06-18-2009 |
20090174812 | Motion-compressed temporal interpolation - The motion-compensated temporal interpolation using an optical flow defined in an interpolation frame from a subsequent frame, and interpolating from either the prior or the subsequent frame depending upon the divergence of the optical flow. | 07-09-2009 |
20110026596 | Method and System for Block-Based Motion Estimation for Motion-Compensated Frame Rate Conversion - Methods for coherent block-based motion estimation for motion-compensated frame rate conversion of decoded video sequences are provided. In some of the disclosed methods, motion vectors are estimated for each block in a decoded frame in both raster scan order and reverse raster scan order using prediction vectors from selected spatially and temporally neighboring blocks. Further, in some of the disclosed methods, a spatial coherence constraint that detects and removes motion vector crossings is applied to the motion vectors estimated for each block in a frame to reduce halo artifacts in the up-converted video sequence. In addition, in some of the disclosed methods, post processing is performed on estimated motion vectors to improve the coherence of the motion vectors. This post-processing includes application of vector median filters to the estimated motion vectors for a frame and/or application of a sub-block motion refinement to increase the density of the motion field. | 02-03-2011 |
20110176014 | Video Stabilization and Reduction of Rolling Shutter Distortion - A method of processing a digital video sequence is provided that includes estimating compensated motion parameters and compensated distortion parameters (compensated M/D parameters) of a compensated motion/distortion (M/D) affine transformation for a block of pixels in the digital video sequence, and applying the compensated M/D affine transformation to the block of pixels using the estimated compensated M/D parameters to generate an output block of pixels, wherein translational and rotational jitter in the block of pixels is stabilized in the output block of pixels and distortion due to skew, horizontal scaling, vertical scaling, and wobble in the block of pixels is reduced in the output block of pixels. | 07-21-2011 |
20110182510 | Methods and Systems for Image Noise Filtering - Methods and systems for image noise filtering are provided. One method of image noise filtering includes generating a plurality of sub-images of a digital image, applying a noise filter with small support to each sub-image, and generating a filtered digital image by merging the filtered sub-images. Another method of image noise filtering includes receiving a digital image including a plurality of color channels in the Bayer domain, applying a strong noise filter to each color channel to generate filtered color channels, computing a luminance image from the digital image, applying a weak noise filter to the luminance image to generate a filtered luminance image, computing a luminance recovery factor map using the luminance image and the filtered luminance image, and computing output color channels of the digital image using the filtered color channels and the luminance recovery factor map. | 07-28-2011 |
20110242422 | Ghosting Artifact Reduction in Temporal Noise Filtering - A method of noise filtering of a digital video sequence to reduce ghosting artifacts, the method including computing motion values for pixels in a frame of the digital video sequence based on a reference frame, computing blending factors for the pixels based on the motion values, generating filtered output pixel values by applying the blending factors to corresponding pixel values in the reference frame and the frame, wherein selected filtered output pixel values are converged toward corresponding pixel values in the frame to reduce ghosting artifacts, and outputting the filtered frame. | 10-06-2011 |
Patent application number | Description | Published |
20080300436 | Selective hydrogenation catalyst and methods of making and using same - A method for producing a selective hydrogenation catalyst for hydrogenating a highly unsaturated hydrocarbon to an unsaturated hydrocarbon comprising contacting an inorganic catalyst support with a chlorine-containing compound to form a chlorided catalyst support and adding palladium to the chlorided catalyst support to form a supported-palladium composition. A selective hydrogenation catalyst for hydrogenating a highly unsaturated hydrocarbon to an unsaturated hydrocarbon formed by the method comprising contacting an inorganic catalyst support with a chlorine-containing compound to form a chlorided catalyst support and adding palladium to the chlorided catalyst support to form a supported-palladium composition. A method of selectively hydrogenating a highly unsaturated hydrocarbon to an unsaturated hydrocarbon comprising contacting the highly unsaturated hydrocarbon with a selective hydrogenation catalyst composition produced by contacting an inorganic catalyst support with a chlorine-containing compound to form a chlorided catalyst support and adding palladium to the chlorided catalyst support to form a supported-palladium composition. | 12-04-2008 |
20100228065 | Selective Hydrogenation Catalyst and Methods of Making and Using Same - A composition comprising a supported hydrogenation catalyst comprising palladium and an organophosphorous compound, the supported hydrogenation catalyst being capable of selectively hydrogenating highly unsaturated hydrocarbons to unsaturated hydrocarbons. A method of making a selective hydrogenation catalyst comprising contacting a support with a palladium-containing compound to form a palladium supported composition, contacting the palladium supported composition with an organophosphorus compound to form a catalyst precursor, and reducing the catalyst precursor to form the catalyst. A method of selectively hydrogenating highly unsaturated hydrocarbons to an unsaturated hydrocarbon enriched composition comprising contacting a supported catalyst comprising palladium and an organophosphorous compound with a feed comprising highly unsaturated hydrocarbon under conditions suitable for hydrogenating at least a portion of the highly unsaturated hydrocarbon feed to form the unsaturated hydrocarbon enriched composition. | 09-09-2010 |
20140107383 | Selective Hydrogenation Catalyst and Methods of Making and Using Same - A composition comprising a supported hydrogenation catalyst comprising palladium and an organophosphorous compound, the supported hydrogenation catalyst being capable of selectively hydrogenating highly unsaturated hydrocarbons to unsaturated hydrocarbons. A method of making a selective hydrogenation catalyst comprising contacting a support with a palladium-containing compound to form a palladium supported composition, contacting the palladium supported composition with an organophosphorus compound to form a catalyst precursor, and reducing the catalyst precursor to form the catalyst. A method of selectively hydrogenating highly unsaturated hydrocarbons to an unsaturated hydrocarbon enriched composition comprising contacting a supported catalyst comprising palladium and an organophosphorous compound with a feed comprising highly unsaturated hydrocarbon under conditions suitable for hydrogenating at least a portion of the highly unsaturated hydrocarbon feed to form the unsaturated hydrocarbon enriched composition. | 04-17-2014 |
20140127593 | METAL-AIR BATTERY SYSTEM WITH DETACHABLE ANODE AND CATHODE COMPARTMENTS - The metal-air battery system of this invention has a detachable anode compartment and cathode compartment for producing electric current, wherein the anode compartment and the cathode compartment are pressed into contact when the battery is put in use to generate electric power; and the anode compartment and the cathode compartment are separated when the battery is not in use to generate electric power. The anode compartment also has an injection device to inject water mist to maintain the moisture level of the metal gel inside the anode compartment. The metal-air battery system of this invention will extend the battery storage life significantly as compared to conventional metal-air battery. In addition, the metal-air battery system of this invention makes replacing anode conveniently so that the battery system can be re-used continuously. | 05-08-2014 |
20140221197 | Selective Hydrogenation Catalyst and Methods of Making and Using Same - A method for producing a selective hydrogenation catalyst for hydrogenating a highly unsaturated hydrocarbon to an unsaturated hydrocarbon comprising contacting an inorganic catalyst support with a chlorine-containing compound to form a chlorided catalyst support and adding palladium to the chlorided catalyst support to form a supported-palladium composition. A selective hydrogenation catalyst for hydrogenating a highly unsaturated hydrocarbon to an unsaturated hydrocarbon formed by the method comprising contacting an inorganic catalyst support with a chlorine-containing compound to form a chlorided catalyst support and adding palladium to the chlorided catalyst support to form a supported-palladium composition. A method of selectively hydrogenating a highly unsaturated hydrocarbon to an unsaturated hydrocarbon comprising contacting the highly unsaturated hydrocarbon with a selective hydrogenation catalyst composition produced by contacting an inorganic catalyst support with a chlorine-containing compound to form a chlorided catalyst support and adding palladium to the chlorided catalyst support to form a supported-palladium composition. | 08-07-2014 |
20150197464 | Selective Hydrogenation Catalyst and Methods of Making and Using Same - A composition comprising a supported hydrogenation catalyst comprising palladium and an organophosphorous compound, the supported hydrogenation catalyst being capable of selectively hydrogenating highly unsaturated hydrocarbons to unsaturated hydrocarbons. A method of making a selective hydrogenation catalyst comprising contacting a support with a palladium-containing compound to form a palladium supported composition, contacting the palladium supported composition with an organophosphorus compound to form a catalyst precursor, and reducing the catalyst precursor to form the catalyst. A method of selectively hydrogenating highly unsaturated hydrocarbons to an unsaturated hydrocarbon enriched composition comprising contacting a supported catalyst comprising palladium and an organophosphorous compound with a feed comprising highly unsaturated hydrocarbon under conditions suitable for hydrogenating at least a portion of the highly unsaturated hydrocarbon feed to form the unsaturated hydrocarbon enriched composition. | 07-16-2015 |
20150380786 | METAL-AIR BATTERY - A metal-air battery includes an anode portion comprising at least a metal gel and an electrolyte. A mesh screen is disposed on the anode portion. The mesh screen is configured for substantially holding the metal gel within the anode portion. A cathode portion includes at least a current carrier and a cathode catalyst. A separator is disposed between the anode portion and the cathode portion for mitigating leakage of the electrolyte. A gate device is disposed between the anode portion and the cathode portion. The gate device has an open state to enable a contact of the anode portion and the cathode portion for activating a generation of electrical power, and a closed state to separate the contact of the anode portion and the cathode portion to inhibit the generation of electrical power for storing the metal-air battery. | 12-31-2015 |