Patent application number | Description | Published |
20130037898 | Memory Array Including Magnetic Random Access Memory Cells and Oblique Field Lines - A memory device includes a first plurality of magnetic random access memory (MRAM) cells positioned along a first direction, and a first bit line electrically connected to the first plurality of MRAM cells, the bit line oriented in the first direction. The device includes a first plurality of field lines oriented in a second direction different from the first direction, the first plurality of field lines being spaced such that only a corresponding first one of the first plurality of MRAM cells is configurable by each of the first plurality of field lines. The device includes a second plurality of field lines oriented in a third direction different from the first direction and the second direction, the second plurality of field lines being spaced such that only a corresponding second one of the first plurality of MRAM cells is configurable by each of the second plurality of field lines. | 02-14-2013 |
20130241536 | Magnetic Logic Units Configured to Measure Magnetic Field Direction - An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device. | 09-19-2013 |
20150077095 | Magnetic Logic Units Configured to Measure Magnetic Field Direction - An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device. | 03-19-2015 |
20150077096 | Magnetic Logic Units Configured to Measure Magnetic Field Direction - An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device. | 03-19-2015 |
20150077097 | Magnetic Logic Units Configured to Measure Magnetic Field Direction - An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device. | 03-19-2015 |
20150077098 | Magnetic Logic Units Configured to Measure Magnetic Field Direction - An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device. | 03-19-2015 |
Patent application number | Description | Published |
20090027080 | Low leakage and data retention circuitry - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 01-29-2009 |
20100060319 | LOW LEAKAGE AND DATA RETENTION CIRCUITRY - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 03-11-2010 |
20110260785 | Low Leakage and Data Retention Circuitry - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 10-27-2011 |
20130027125 | LOW LEAKAGE AND DATA RETENTION CIRCUITRY - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 01-31-2013 |
20140375354 | Low Leakage and Data Retention Circuitry - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 12-25-2014 |
Patent application number | Description | Published |
20080276105 | POWER MANAGERS FOR AN INTEGRATED CIRCUIT - A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands. | 11-06-2008 |
20090152948 | POWER MANAGERS FOR AN INTEGRATED CIRCUIT - A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands. | 06-18-2009 |
20120043812 | Power Managers for an Integrated Circuit - A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands. | 02-23-2012 |
20120256485 | Power Managers for an Integrated Circuit - A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands. | 10-11-2012 |
20140333134 | POWER MANAGERS FOR AN INTEGRATED CIRCUIT - A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands. | 11-13-2014 |
20160087608 | POWER MANAGERS FOR AN INTEGRATED CIRCUIT - Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level. | 03-24-2016 |
Patent application number | Description | Published |
20110245699 | SYSTEMS AND METHODS RELATED TO ST SEGMENT MONITORING BY AN IMPLANTABLE MEDICAL DEVICE - Cardiac activity is sensed over a plurality of heart beats defining a beat set. For each beat in the set, it is determined whether the beat is a non-classified beat (e.g., paced beat, a beat outside of a specified heart rate range or a PVC), or a classified beat. For each classified beat, it is determined whether the beat is a non-detect beat, a minor beat or a major beat. Counts of classified beats, non-classified beats, major beats, minor beats, and non-detect beats are maintained. The beat set is declared to be one of a non-classified set, a major set, a minor set or a non-detect set based on the relative counts of classified beats, non-classified beats, major beats, minor beats, and non-detect beats. Over a period of time, counts of beat-set types are maintained and entry into and exit from ST episodes are determined based on these beat-set counts. | 10-06-2011 |
20120101544 | NON-PROGRAMMING ACTIVATION DEVICE FOR SWITCHING MODES OF AN IMPLANTABLE MEDICAL DEVICE AND METHODS FOR SAME - When a medical procedure is performed on a patient in whom an implantable medical device is implanted, the medical procedure may have undesired effects on the medical device, such as triggering a response that initiates therapy by the device that is unnecessary and potentially dangerous to the patient. Systems and methods may facilitate performing of such medical procedures on such patients by automatically reprogramming the medical device, monitoring for one or more detectable characteristics associated with the medical procedure to be performed, and automatically restoring normal operation of the IMD after the medical procedure is completed. | 04-26-2012 |
20150290455 | PROTECTIVE PATCH FOR PROTECTING THE IMPLANT SITE OF A TRIAL NEUROSTIMULATION LEAD - A protective patch or bandage is provided for use with an implantable trial neurostimulation lead for implant within a patient. In one example, the lead is routed through the patch to a trial neurostimulation generator. In another example, the patch includes an internal electrical connector for connecting the trial neurostimulation lead to a connection line from the trial neurostimulation generator. In either case, the patch is sealed over an implant site to protect and hygienically isolate the site. A central chamber of the patch is provided to hold medical gauze and to further hold a coiled portion of the neurostimulation lead. In some examples, the patient can shower while wearing the protective patch. | 10-15-2015 |
20160067502 | ENCLOSURE FOR PROTECTING A TRIAL NEUROSTIMULATION GENERATOR FROM CONTAMINATION - Disclosed herein is a disposable enclosure for use with a trial neurostimulation device configured to electrically couple with a neurostimulation lead for implant within a patient. The trial neurostimulation device includes a pulse generator portion. The disposable enclosure includes a first wall structure, a second wall structure opposite the first wall structure, a volume between the first and second wall structures, and a header. The volume is configured to receive therein the pulse generator portion. The header is configured to electrically couple with the neurostimulation lead. The header is supported in the disposable enclosure adjacent the volume and configured to electrically couple with the pulse generator portion when the pulse generator portion is located in the volume. | 03-10-2016 |