Patent application number | Description | Published |
20090083478 | INTEGRATED MEMORY MANAGEMENT AND MEMORY MANAGEMENT METHOD - An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory. | 03-26-2009 |
20090122598 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell. | 05-14-2009 |
20100064111 | INFORMATION PROCESSING DEVICE INCLUDING MEMORY MANAGEMENT DEVICE MANAGING ACCESS FROM PROCESSOR TO MEMORY AND MEMORY MANAGEMENT METHOD - A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address. | 03-11-2010 |
20110131366 | MEMORY MANAGEMENT UNIT AND MEMORY MANAGEMENT METHOD - According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error flag to issue error data when the data is not stored in the second memory, and reading, into a free space of the second memory, the data to be accessed in the first memory. | 06-02-2011 |
20120008372 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell. | 01-12-2012 |
20120124290 | Integrated Memory Management and Memory Management Method - An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory. | 05-17-2012 |
20120191900 | MEMORY MANAGEMENT DEVICE - A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory. | 07-26-2012 |
20120216003 | SEMICONDUCTOR DEVICE AND MEMORY PROTECTION METHOD - According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets. | 08-23-2012 |
20120246397 | STORAGE DEVICE MANAGEMENT DEVICE AND METHOD FOR MANAGING STORAGE DEVICE - According to one embodiment, a storage device management device is connected to a random access memory and a first storage device. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has stored the copied data is released. When stored on the random access memory, the read data is read from the random access memory to the processor. When stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor. | 09-27-2012 |
20130163755 | PROTECTION METHOD, DECRYPTION METHOD, PLAYER, STORAGE MEDIUM, AND ENCRYPTION APPARATUS OF DIGITAL CONTENT - A digital content protection method includes distributing, together with an encrypted content, an encrypted protected program key, a protected content key, and a protected code including an individual instruction code, at least some elements of which are designed according to a unique operation code specification for each content player or for each content player group. | 06-27-2013 |
20130198437 | MEMORY MANAGEMENT DEVICE AND MEMORY MANAGEMENT METHOD - In an embodiment, a device includes a first unit, a second unit, and a third unit. The first unit generates a write address representing a write position to sequentially store sequential data from a processor to a nonvolatile main memory. The second unit generates order information representing a degree of newness of write. The third unit writes sequentially writes the sequential data at the write address with the order information. | 08-01-2013 |
20130254471 | DEVICE AND MEMORY SYSTEM FOR MEMORY MANAGEMENT USING ACCESS FREQUENCY INFORMATION - An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory. | 09-26-2013 |
20150058588 | SEMICONDUCTOR DEVICE AND MEMORY PROTECTION METHOD - According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets. | 02-26-2015 |
20150071155 | COMMUNICATION APPARATUS AND COMMUNICATION METHOD - According to the embodiments, a communication apparatus stores therein an operation mode indicating whether the communication apparatus is a publisher or a subscriber, and includes a message processing unit that generates a transmission message and analyzes a reception message and a nonvolatile memory. When the communication apparatus is subscriber, the communication apparatus sends a repair message to request a retransmission of a data chunk not successively received. When the communication apparatus is publisher, the communication apparatus selectively retransmits the data chunk based on the repair message. | 03-12-2015 |
20150071156 | COMMUNICATION APPARATUS AND COMMUNICATION METHOD - According to the embodiments, when a communication apparatus is a publisher, a transmission message including a first identifier is transmitted using first transmission power, when the communication apparatus is a subscriber, data of a reception message including the first identifier is stored in a nonvolatile memory, when at least a part of the reception message cannot be received, a repair message for requesting retransmission of the reception message is transmitted from a wireless interface unit using second transmission power, and when there is no response, a repair message is transmitted using third transmission power that is larger than the second transmission power. | 03-12-2015 |