Patent application number | Description | Published |
20100102362 | SOLID-STATE IMAGE PICKUP ELEMENT, SOLID-STATE IMAGE PICKUP DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a ratio of a surface area of a light-receiving section to the overall surface area of one pixel. The solid-state image pickup element comprises a first-conductive type planar semiconductor layer formed on a second-conductive type planar semiconductor layer, a hole portion formed in the first-conductive type planar semiconductor layer to define a hole therein, a first-conductive type high-concentration impurity region formed in a bottom wall of the hole portion, a first-conductive type high-concentration impurity-doped element isolation region formed in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region, a second-conductive type photoelectric conversion region formed beneath the first-conductive type high-concentration impurity region and in a part of a lower region of the remaining part of the sidewall of the hole portion, and adapted to undergo a change in charge amount upon receiving light, a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film, a second-conductive type CCD channel region formed in a top surface of the first-conductive type planar semiconductor layer and in a part of an upper region of the remaining part of the sidewall of the hole portion, and a read channel formed in a region of the first-conductive type planar semiconductor layer sandwiched between the second-conductive type photoelectric conversion region and the second-conductive type CCD channel region. | 04-29-2010 |
20100187600 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer. | 07-29-2010 |
20100194438 | SEMICONDUCTOR DEVICE - It is intended to provide a semiconductor device which comprises an SGT-based, highly-integrated, high-speed, at least two-stage CMOS inverter cascade circuit configured to allow a pMOS SGT to have a gate width two times greater than that of an nMOS SGT. A semiconductor device of the present invention comprises a CMOS inverter cascade circuit having at least two-stage CMOS inverter, wherein: a first CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 1st column and an intersection of the 2nd row and the 1st column, and an nMOS SGT arranged at an intersection of the 1st row and the 2nd column; and a second CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 3rd column and an intersection of the 2nd row and the 3rd column, and an nMOS SGT arranged at an intersection of the 2nd row and the 2nd column. An output terminal line is connected to an input terminal line, wherein the output terminal line is arranged to interconnect a drain diffusion layer of each of the two SGTS at respective ones of the intersection of the 1st row and the intersection of the 2nd row and the 1st column and the 1st column, and a drain diffusion layer of the SGT at the intersection of the 1st row and the 2nd column, through an island-shaped semiconductor lower layer, and the an input terminal line is arranged to interconnect a gate of each of the two SGTs at respective ones of the intersection of the 1st row and the 3rd column and the intersection of the 2nd row and the 3rd column, and a gate of the SGT at and the intersecting of the 2nd row and 2nd column. | 08-05-2010 |
20100200731 | SOLID-STATE IMAGING DEVICE - It is intended to provide a CMOS image sensor with a high degree of pixel integration. A solid-state imaging device comprises a signal line ( | 08-12-2010 |
20100207199 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer. | 08-19-2010 |
20100210079 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - It is intended to provide an SGT production method capable of obtaining a structure for reducing a resistance of a source, drain and gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor to be obtained. The method comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a dummy gate dielectric film and a dummy gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a first dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode, through a gate dielectric film; forming a first dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on each of the second-conductive-type semiconductor layers formed in the upper portion of and underneath the pillar-shaped first-conductive-type semiconductor layer; removing the dummy gate dielectric film and the dummy gate electrode and forming a high-k gate dielectric film and a metal gate electrode. | 08-19-2010 |
20100219457 | SOLID-STATE IMAGING DEVICE - It is an object to provide an image sensor having a sufficiently-large ratio of a surface area of a light-receiving section to an overall surface area of one pixel. This object is achieved by a solid-state imaging device comprising: a signal line formed on a substrate; an island-shaped semiconductor arranged on the signal line; and a pixel selection line connected to a top of the island-shaped semiconductor, wherein the island-shaped semiconductor includes: a first semiconductor layer formed as a bottom portion of the island-shaped semiconductor and connected to the signal line; a second semiconductor layer formed above and adjacent to the first semiconductor layer; a gate connected to the second semiconductor layer through a dielectric film; a charge storage section comprised of a third semiconductor layer connected to the second semiconductor layer and adapted, in response to receiving light, to undergo a change in amount of electric charges therein; and a fourth semiconductor layer formed above and adjacent to the second and third semiconductor layers, and wherein the pixel selection line is comprised of a transparent conductive film, and a part of the gate is disposed inside a depression formed in a sidewall of the second semiconductor layer. | 09-02-2010 |
20100219464 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the gate electrode; forming a contact on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; and forming a contact on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer. | 09-02-2010 |
20100244140 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit. The object is achieved by a semiconductor device which comprises an island-shaped semiconductor layer, a first gate dielectric film surrounding a periphery of the island-shaped semiconductor layer, a gate electrode surrounding a periphery of the first gate dielectric film, a second gate dielectric film surrounding a periphery of the gate electrode, a tubular semiconductor layer surrounding a periphery of the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer disposed on top of the island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer disposed underneath the island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer disposed on top of the tubular semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer disposed underneath the tubular semiconductor layer. | 09-30-2010 |
20100264485 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a first columnar semiconductor layer on a first flat semiconductor layer; forming a first semiconductor layer of a second conductive type in a lower portion of the first columnar semiconductor layer; forming a first insulating film around a lower sidewall of the first columnar silicon layer; forming a gate insulating film and a gate electrode around the first columnar silicon layer; forming a sidewall-shaped second insulating film to surround an upper sidewall of the first columnar silicon layer; forming a semiconductor layer of a first conductive type between the first semiconductor layer of the second conductive type and a second semiconductor layer of the second conductive type; and forming a metal-semiconductor compound on an upper surface of the first semiconductor layer of the second conductive type. | 10-21-2010 |
20100308422 | SEMICONDUCTOR DEVICE - The object to provide a highly-integrated SGT-based SRAM is achieved by forming an SRAM using an inverter which comprises a first island-shaped semiconductor layer, a first gate dielectric film in contact with a periphery of the first island-shaped semiconductor layer, a first gate electrode having one surface in contact with the first gate dielectric film, a second gate dielectric film in contact with another surface of the first gate electrode, a first arc-shaped semiconductor layer in contact with the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer arranged on a top of the first island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer arranged underneath the first island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer arranged on a top of the first arc-shaped semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer arranged underneath the first arc-shaped semiconductor layer. | 12-09-2010 |
20110042740 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate. | 02-24-2011 |
20110062515 | SEMICONDUCTOR DEVICE - A first gate electrode surrounding the periphery of the first gate insulating film, a second gate insulating film surrounding the periphery of the first gate electrode, a first columnar silicon layer surrounding the periphery of the second gate insulating film, a first upper part high concentration semiconductor layer of the first conductivity type formed in the upper part of the first island-shaped silicon layer, a second lower part high concentration semiconductor layer of the first conductivity type formed in the lower part of the first island-shaped silicon layer, a first upper part high concentration semiconductor layer of the second conductivity type formed in the upper part of the first columnar silicon layer, and a second lower part high concentration semiconductor layer of the second conductivity type formed in the lower part of the first columnar silicon layer. | 03-17-2011 |
20110062521 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention comprises a first transistor and a second transistor, and functions as an inverter. The first transistor includes an island semiconductor layer, a first gate insulating film surrounding the periphery of the island semiconductor layer, a gate electrode surrounding the periphery of the first gate insulating film, p+-type semiconductor layers formed in the upper and lower part of the island semiconductor layer, respectively. The second transistor includes the gate electrode, a second gate insulating film surrounding a part of the periphery of the gate electrode, an arcuate semiconductor layer contacting a part of the periphery of the second gate insulating film, n+-type semiconductor layers formed in the upper and lower part of the arcuate semiconductor layer, respectively. A first contact electrically connects the p+-type semiconductor layer in the first transistor and the n+-type semiconductor layer in the second transistor. | 03-17-2011 |
20110079841 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which has a CMOS inverter circuit and which can accomplish high-integration by configuring an inverter circuit with a columnar structural body. A semiconductor device includes a columnar structural body which is arranged on a substrate and which comprises a p-type silicon, an n-type silicon, and an oxide arranged between the p-type silicon and the n-type silicon and running in the vertical direction to the substrate, n-type high-concentration silicon layers arranged on and below the p-type silicon, p-type high-concentration silicon layers arrange on and below the n-type silicon, an insulator which surrounds the p-type silicon, the n-type silicon, and the oxide, and which serves as a gate insulator, and a conductive body which surrounds the insulator and which serves as a gate electrode. | 04-07-2011 |
20110086460 | SOLID-STATE IMAGE PICKUP ELEMENT, SOLID-STATE IMAGE PICKUP DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a ratio of a surface area of a light-receiving section to the overall surface area of one pixel. The solid-state image pickup element comprises a first-conductive type planar semiconductor layer formed on a second-conductive type planar semiconductor layer, a hole portion formed in the first-conductive type planar semiconductor layer to define a hole therein, a first-conductive type high-concentration impurity region formed in a bottom wall of the hole portion, a first-conductive type high-concentration impurity-doped element isolation region formed in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region, a second-conductive type photoelectric conversion region formed beneath the first-conductive type high-concentration impurity region and in a part of a lower region of the remaining part of the sidewall of the hole portion, and adapted to undergo a change in charge amount upon receiving light, a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film, a second-conductive type CCD channel region formed in a top surface of the first-conductive type planar semiconductor layer and in a part of an upper region of the remaining part of the sidewall of the hole portion, and a read channel formed in a region of the first-conductive type planar semiconductor layer sandwiched between the second-conductive type photoelectric conversion region and the second-conductive type CCD channel region. | 04-14-2011 |
20110089496 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD - The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer. | 04-21-2011 |
20110118003 | GAMING MACHINE AND CONTROL METHOD THEREOF - To provide a gaming machine and a control method therefor, having a new entertainment characteristics, a slot machine | 05-19-2011 |
20110207260 | METHOD OF PRODUCING A SOLID-STATE IMAGE SENSING DEVICE INCLUDING SOLID-STATE IMAGE SENSOR HAVING A PILAR-SHAPED SEMICONDUCTOR LAYER - It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving portion (photodiode) to an area of one pixel is increased. There is provided a solid-state image sensor, including: a first conductive type semiconductor layer; a first conductive type pillar-shaped semiconductor layer formed on the first conductive type semiconductor layer; a second conductive type photoelectric conversion region formed on the top of the first conductive type pillar-shaped semiconductor layer, an electric charge amount of the photoelectric conversion region being changed by light; and a high-concentrated impurity region of the first conductive type formed on a surface of the second conductive type photoelectric conversion region, the impurity region being spaced apart from a top end of the first conductive type pillar-shaped semiconductor layer by a predetermined distance, wherein a transfer electrode is formed on the side of the first conductive type pillar-shaped semiconductor layer via a gate insulating film, a second conductive type CCD channel region is formed below the transfer electrode, and a read channel is formed in a region between the second conductive type photoelectric conversion region and the second conductive type CCD channel region. | 08-25-2011 |
20110220972 | SOLID-STATE IMAGE PICKUP ELEMENT, SOLID-STATE IMAGE PICKUP DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a ratio of a surface area of a light-receiving section to the overall surface area of one pixel. The solid-state image pickup element comprises a first-conductive type planar semiconductor layer formed on a second-conductive type planar semiconductor layer, a hole portion formed in the first-conductive type planar semiconductor layer to define a hole therein, a first-conductive type high-concentration impurity region formed in a bottom wall of the hole portion, a first-conductive type high-concentration impurity-doped element isolation region formed in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region, a second-conductive type photoelectric conversion region formed beneath the first-conductive type high-concentration impurity region and in a part of a lower region of the remaining part of the sidewall of the hole portion, and adapted to undergo a change in charge amount upon receiving light, a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film, a second-conductive type CCD channel region formed in a top surface of the first-conductive type planar semiconductor layer and in a part of an upper region of the remaining part of the sidewall of the hole portion, and a read channel formed in a region of the first-conductive type planar semiconductor layer sandwiched between the second-conductive type photoelectric conversion region and the second-conductive type CCD channel region. | 09-15-2011 |
20110241122 | SEMICONDUCTOR DEVICE - There is provided a high-integrated complementary metal-oxide semiconductor static random-access memory including an inverter. The inverter includes: a first pillar that is formed by integrating a first-conductivity-type semiconductor, a second-conductivity-type semiconductor, and an insulating material disposed between the first-conductivity-type semiconductor and the second-conductivity-type semiconductor, and that vertically extends with respect to a substrate; a first second-conductivity-type high-concentration semiconductor disposed on the first-conductivity-type semiconductor; a second second-conductivity-type high-concentration semiconductor disposed under the first-conductivity-type semiconductor; a first first-conductivity-type high-concentration semiconductor disposed on the second-conductivity-type semiconductor; a second first-conductivity-type high-concentration semiconductor disposed under the second-conductivity-type semiconductor; a gate insulating material formed around the first pillar; and a gate conductive material formed around the gate insulating material. | 10-06-2011 |
20110303966 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate. | 12-15-2011 |
20110303973 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD - The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film. | 12-15-2011 |
20110303985 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer. | 12-15-2011 |
20120025291 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line. | 02-02-2012 |
20120025292 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the Si substrate side, a floating gate surrounding the outer periphery of the channel region with a tunnel insulating film interposed therebetween, a control gate surrounding the outer periphery of the floating gate with an inter-polysilicon insulating film interposed therebetween, and a control gate line connected to the control gate and extending in a predetermined direction. The floating gate extends to regions below and above the control gate and to a region below the control gate line. The inter-polysilicon insulating film is interposed between the floating gate and the upper surface, lower surface, and inner side surface of the control gate and between the control gate line and a portion of the floating gate that extends to the region below the control gate line. | 02-02-2012 |
20120139035 | SEMICONDUCTOR DEVICE - A semiconductor memory device includes a static memory cell having six MOS transistors arranged on a substrate. The six MOS transistors include first and second NMOS access transistors, third and fourth NMOS driver transistors, and first and second PMOS load transistors. Each of the first and second NMOS access transistors has a first diffusion layer, a pillar-shaped semiconductor layer, and a second diffusion layer arranged vertically on the substrate in a hierarchical manner. Each of the third and fourth NMOS driver transistors has a third diffusion layer, a pillar-shaped semiconductor layer, and a fourth diffusion layer arranged vertically on the substrate in a hierarchical manner. The lengths between the upper ends of the third diffusion layers and the lower ends of the fourth diffusion layers are shorter than the lengths between the upper ends of the first diffusion layer and the lower ends of the second diffusion layers. | 06-07-2012 |
20120142154 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - An SGT production method includes forming a pillar-shaped first-conductive-type semiconductor layer and forming a second-conductive-type semiconductor layer underneath the first-conductive-type semiconductor layer. A dummy gate dielectric film and a dummy gate electrode are formed around the first-conductive-type semiconductor layer and a first dielectric film is formed on an upper region of a sidewall of the first-conductive-type semiconductor layer in contact with a top of the gate electrode. A first dielectric film is formed on a sidewall of the gate electrode and a second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer. A second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer and a metal-semiconductor compound is formed on each of the second-conductive-type semiconductor layers. The dummy gate dielectric film and the dummy gate electrode are removed and a high-k gate dielectric film and a metal gate electrode are formed. | 06-07-2012 |
20120181618 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first driver transistor includes a first gate insulating film that surrounds a periphery of a first island-shaped semiconductor, a first gate electrode having a first surface that is in contact with the first gate insulating film, and first and second first-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first island-shaped semiconductor, respectively. A first load transistor includes a second gate insulating film having a first surface that is in contact with a second surface of the first gate electrode, a first arcuate semiconductor formed so as to be in contact with a portion of a second surface of the second gate insulating film, and first and second second-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first arcuate semiconductor, respectively. A first gate line extends from the first gate electrode and is made of the same material as the first gate electrode. | 07-19-2012 |
20120252547 | GAMING MACHINE RUNNING COMPETING GAME BETWEEN GAMING TERMINALS - A gaming machine, at the time of the result of the base game associated with the payout, determines whether at least a competing game condition associated with the payout is satisfied or not. In the case where it is determined that the competing game condition is satisfied, the gaming machine sets the neighboring gaming terminals as opponents. When the opponent participates in the competing game for winning a payout by competing against the opponent, the gaming machine repeatedly runs an auxiliary unit game as a trigger of running a competing game. In the auxiliary unit game, pieces move on a plurality of chained frames scroll-displayed on the common display. In the case where the frame on which the piece is stopped corresponds to the trigger of the competing game, the competing game is run. | 10-04-2012 |
20120252561 | GAMING MACHINE RUNNING COMPETING GAME BETWEEN GAMING TERMINALS - The present invention provides a gaming machine including gaming terminals having high payout rate without increasing loss on the management side. When a result of a base game associated with a payout is obtained, the gaming machine determines whether at least a competing game condition associated with the payout is satisfied or not and, when it is determined that the competing game condition is satisfied, sets neighboring gaming terminals as opponents. When the opponent participates in a competing game, a competing game for winning a payout by competing against the opponent is run. According to a result of the competing game, at least a part of the payout is given to the winner of the competing game, and no payout is given to the loser of the competing game. | 10-04-2012 |
20120264265 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit. The object is achieved by a semiconductor device which comprises an island-shaped semiconductor layer, a first gate dielectric film surrounding a periphery of the island-shaped semiconductor layer, a gate electrode surrounding a periphery of the first gate dielectric film, a second gate dielectric film surrounding a periphery of the gate electrode, a tubular semiconductor layer surrounding a periphery of the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer disposed on top of the island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer disposed underneath the island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer disposed on top of the tubular semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer disposed underneath the tubular semiconductor layer. | 10-18-2012 |
20120299068 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer. | 11-29-2012 |
20130095625 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate. | 04-18-2013 |
20130113037 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact. | 05-09-2013 |
20130130772 | GAMING MACHINE AND CONTROL METHOD THEREOF - To provide a gaming machine and a control method therefor, having a new entertainment characteristics, a slot machine | 05-23-2013 |
20130130773 | GAMING MACHINE AND CONTROL METHOD THEREOF - To provide a gaming machine and a control method therefor, having a new entertainment characteristics, a slot machine | 05-23-2013 |
20130130775 | GAMING MACHINE AND CONTROL METHOD THEREOF - To provide a gaming machine and a control method therefor, having a new entertainment characteristics, a slot machine | 05-23-2013 |
20130140627 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes. | 06-06-2013 |
20130146964 | METHOD OF PRODUCING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes the steps of forming a planar silicon layer, first and second pillar-shaped silicon layers on a silicon substrate; forming a gate insulating film, depositing a metal film and a polysilicon around the gate insulating film, conducting planarization, conducting etching to expose upper portions of the first and second pillar-shaped silicon layers, forming first and second insulating film sidewalls, and forming first and second gate electrodes and a gate line; forming n-type diffusion layers in upper and lower portions of the first pillar-shaped silicon layer, and forming p-type diffusion layers in upper and lower portions of the second pillar-shaped silicon layer; forming a third insulating film sidewall on side walls of the first and second insulating film sidewalls, the first and second gate electrodes, and the gate line; and forming a silicide. | 06-13-2013 |
20130153989 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes. | 06-20-2013 |
20130228869 | SEMICONDUCTOR DEVICE - An SGT-based static memory cell which is a six-transistor SRAM cell includes an SGT driver transistor including a first gate electrode surrounding a first gate insulating film and composed of at least a metal; an SGT selection transistor including a second gate electrode surrounding a second gate insulating film and composed of at least a metal; an SGT load transistor including a third gate electrode surrounding a third gate insulating film and composed of at least a metal; and a gate wire connected to the second gate electrode. An island-shaped semiconductor layer of the driver transistor has a peripheral length that is less than twice that of an island-shaped semiconductor layer of the selection transistor. A voltage applied to the second gate electrode is lower than a voltage applied to a first-conductivity-type high-concentration semiconductor layer on the upper part of the island-shaped semiconductor layer of the selection transistor. | 09-05-2013 |
20130252413 | SURROUND GATE CMOS SEMICONDUCTOR DEVICE - The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer. | 09-26-2013 |
20130288756 | GAMING MACHINE - A gaming machine with more gaming excitement is provided. The gaming machine includes a cabinet; a lamp body provided on a front surface of the cabinet; a sensor configured to detect a player's gesture with respect to the lamp body; an image display panel configured to execute an effect in sync with the gesture; and a controller used to start a game, the controller starting the detection of the player's gesture by the sensor at a timing corresponding to the state of the game, and while the player's gesture is being detected, executing the effect by the upper image display panel in sync with the detected player's gesture. | 10-31-2013 |
20130288792 | GAMING MACHINE - A gaming machine with more gaming excitement is provided. The gaming machine includes: a cabinet; an upper image display panel which is provided on the cabinet and displays an effect image concerning a game; a lamp body unit which includes a lamp body which is a formed object and a sensor configured to detect the player's gesture with respect to the lamp body and is provided at a position different from the upper image display panel when viewed from the front surface of the cabinet; and a controller used to start the game, and the controller detects the player's gesture by the sensor at a timing corresponding to the state of the game and displays an effect image corresponding to the detected player's gesture on the upper image display panel. | 10-31-2013 |
20130288793 | GAMING MACHINE - A gaming machine with more gaming excitement is provided. The gaming machine includes; a cabinet; an upper image display panel which is provided on the cabinet and is a display displaying an effect image regarding a game; a lamp body which is three-dimensionally formed and is a formed object provided on the cabinet to protrude toward the front surface as compared to at least the lower end of the upper image display panel; a sensor configured to detect the player' gesture with respect to the lamp body; a controller used to start the game, and the controller detects the player's gesture by the sensor at a timing corresponding to the state of the game and displays an effect image corresponding to the detected player's gesture on the upper image display panel. | 10-31-2013 |
20130307037 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact. | 11-21-2013 |
20130307057 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first pillar-shaped silicon layer formed on a planar silicon layer, a gate insulating film formed around the first pillar-shaped silicon layer, a first gate electrode formed around the gate insulating film, a gate line connected to the first gate electrode, a first first-conductivity-type diffusion layer formed in an upper portion of the first pillar-shaped silicon layer, a second first-conductivity-type diffusion layer formed in a lower portion of the first pillar-shaped silicon layer and an upper portion of the planar silicon layer, a first sidewall having a laminated structure of an insulating film and polysilicon and being formed on an upper sidewall of the first pillar-shaped silicon layer and an upper portion of the first gate electrode, and a first contact formed on the first first-conductivity-type diffusion layer and the first sidewall. | 11-21-2013 |
20130307083 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first planar silicon layer, first and second pillar-shaped silicon layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped silicon layer and a center of the second pillar-shaped silicon layer. | 11-21-2013 |
20130328138 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes. | 12-12-2013 |
20140021525 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate. | 01-23-2014 |
20140021588 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD - The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer. | 01-23-2014 |
20140042504 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact. | 02-13-2014 |
20140042526 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT-production method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer, where the pillar-shaped silicon layer has the same width as the fin-shaped silicon layer, forming a gate insulating film around the pillar-shaped silicon layer, forming, around the gate insulating film, a metal film and a polysilicon film thinner than the width of the pillar-shaped silicon layer, forming a third resist for forming a gate line, performing anisotropic etching to form the gate line, depositing a fourth resist, exposing the polysilicon film on a sidewall of an upper portion of the pillar-shaped silicon layer, removing the exposed polysilicon film by etching, removing the fourth resist, removing the metal film by etching, and forming a gate electrode connecting to the gate line. | 02-13-2014 |
20140054681 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes. | 02-27-2014 |
20140070298 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween. | 03-13-2014 |
20140070326 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes. | 03-13-2014 |
20140087812 | GAMING MACHINE AND GAMING METHOD - A game is executed in a normal round, in a first-type free round, and in a second-type free round. The normal round is executed with a first symbol set including a plurality of symbols. The first-type free round is executed with a second symbol set that includes at least one first symbol in addition to the symbols in the first symbol set. The second-type free round is executed with a third symbol set that includes at least one second symbol in addition to the symbols in the first symbol set, the at least one second symbol being different from the at least one first symbol. | 03-27-2014 |
20140091372 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line. | 04-03-2014 |
20140091385 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first pillar-shaped silicon layer formed on a planar silicon layer, a gate insulating film formed around the first pillar-shaped silicon layer, a first gate electrode formed around the gate insulating film, a gate line connected to the first gate electrode, a first first-conductivity-type diffusion layer formed in an upper portion of the first pillar-shaped silicon layer, a second first-conductivity-type diffusion layer formed in a lower portion of the first pillar-shaped silicon layer and an upper portion of the planar silicon layer, a first sidewall having a laminated structure of an insulating film and polysilicon and being formed on an upper sidewall of the first pillar-shaped silicon layer and an upper portion of the first gate electrode, and a first contact formed on the first first-conductivity-type diffusion layer and the first sidewall. | 04-03-2014 |
20140091403 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact. | 04-03-2014 |
20140094252 | SLOT MACHINE INCLUDING A PLURALITY OF VIDEO REEL STRIPS - Provided is a slot machine capable of reducing unfairness which may result between a player who has made an investment and a player who has not made an investment and allowing a player to proceed with a game by making an investment in expectation of a jackpot at ease. Each money amount which is constant is accumulated independently of a number of bets each time betting is conducted, and upon winning a jackpot, a money amount calculated by multiplying a money amount accumulated until then by a multiplying factor based on the number of bets is provided. | 04-03-2014 |
20140097494 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes forming a fin-shaped silicon layer, a first insulating film around the fin-shaped silicon layer, a pillar-shaped silicon layer on the fin-shaped silicon layer, a gate electrode and a gate insulating film around the pillar-shaped silicon layer, a gate line connected to the gate electrode, a first diffusion layer in an upper portion of the pillar-shaped silicon layer, a second diffusion layer in a lower portion of the pillar-shaped silicon layer and an upper portion of the fin-shaped silicon layer, and a first silicide and a second silicide on the first diffusion layer and the second diffusion layer; an interlayer insulating film to expose an upper portion of the pillar-shaped silicon layer; etching the interlayer insulating film to form a contact hole; depositing a metal to form the first contact on the second silicide; and performing etching to form the metal wire. | 04-10-2014 |
20140097500 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer. | 04-10-2014 |
20140117431 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped charge storage layer arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the charge storage layer and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the charge storage layer in such a manner that an insulating film is interposed between the control gate and the charge storage layer. The insulating film is arranged so as to be interposed between the charge storage layer and the upper, lower, and inner side surfaces of the control gate. | 05-01-2014 |
20140131791 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a first step of forming a fin-shaped silicon layer on a silicon substrate using a first resist and forming a first insulating film therearound; and a second step of forming a second insulating film around the fin-shaped silicon layer and etching the second insulating film so as to be left on a side wall of the fin-shaped silicon layer, depositing a third insulating film on the first and second insulating films and the fin-shaped silicon layer, depositing a polysilicon thereon, planarizing a surface thereof, and etching back the polysilicon to expose the third insulating film, forming a second resist, etching the second and third insulating films and then etching the fin-shaped silicon layer and the polysilicon, and removing the second insulating film to form a pillar-shaped silicon layer and a dummy gate formed of the polysilicon. | 05-15-2014 |
20140151767 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact. | 06-05-2014 |
20140203353 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A second step forms a gate insulating film around the pillar-shaped semiconductor layer, a gate electrode around the gate insulating film, and a gate line. A third step forms a first first-conductivity-type diffusion layer in an upper portion of the pillar-shaped semiconductor layer and a second first-conductivity-type diffusion layer in a lower portion of the pillar-shaped semiconductor layer and an upper portion of the fin-shaped semiconductor layer. A fourth step includes depositing, planarizing, and etching-back a first interlayer insulating film to expose an upper portion of the pillar-shaped semiconductor layer, depositing a first metal, and etching the metal to form a first sidewall around the upper portion of the pillar-shaped semiconductor layer. | 07-24-2014 |
20140209998 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pillar-shaped semiconductor having an impurity concentration of 10 | 07-31-2014 |
20140213025 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes. | 07-31-2014 |
20140235321 | GAMING MACHINE AND CONTROL METHOD THEREOF - In a gaming machine, a symbol display device variably displays a plurality of symbols, and an input device inputs an instruction related to a game. A controller executes a normal game in which the symbol display device variably displays and then stop-displays symbols, triggers a bonus game when a plurality of specific symbols are stop-displayed in the normal game, selects any one of a plurality of options by an operation of the input device by a user in the bonus game, and awards a benefit according to the selected option. Further, when the selected option selected in the processing is a specific option, the controller selects another one of the plurality of options by the operation of the input device by the user, and awards a benefit according to the selected another option. | 08-21-2014 |
20140242766 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact. | 08-28-2014 |
20140264560 | SEMICONDUCTOR DEVICE - A SGT-production method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer, where the pillar-shaped silicon layer has the same width as the fin-shaped silicon layer, forming a gate insulating film around the pillar-shaped silicon layer, forming, around the gate insulating film, a metal film and a polysilicon film thinner than the width of the pillar-shaped silicon layer, forming a third resist for forming a gate line, performing anisotropic etching to form the gate line, depositing a fourth resist, exposing the polysilicon film on a sidewall of an upper portion of the pillar-shaped silicon layer, removing the exposed polysilicon film by etching, removing the fourth resist, removing the metal film by etching, and forming a gate electrode connecting to the gate line. | 09-18-2014 |
20140264561 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first fin-shaped silicon layer on a substrate and a second fin-shaped silicon layer on the substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. A silicide in upper portions of n-type and p-type diffusion layers in the upper portions of the first and second fin-shaped silicon layers. A metal gate line is connected to first and second metal gate electrodes and extends in a direction perpendicular to the first fin-shaped silicon layer and the second fin-shaped silicon layer. A first contact is in direct contact with the n-type diffusion layer in the upper portion of the first pillar-shaped silicon layer, and a second contact is in direct contact with the p-type diffusion layer in the upper portion of the second pillar-shaped silicon layer. | 09-18-2014 |
20140323201 | GAMING MACHINE AND CONTROL METHOD THEREOF - As a normal game, symbols to be rearranged on a lower image display panel | 10-30-2014 |
20140339627 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pillar-shaped silicon layer and a first-conductivity-type diffusion layer in an upper portion of the pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and polysilicon resides on an upper sidewall of the pillar-shaped silicon layer. A top of the polysilicon of the sidewall is electrically connected to a top of the first-conductivity-type diffusion layer and has the same conductivity as the diffusion layer. | 11-20-2014 |
20140339628 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer on a silicon substrate and a first insulating film around the fin-shaped silicon layer. A pillar-shaped silicon layer resides on the fin-shaped silicon layer. A gate electrode and gate insulating film surround the pillar-shaped silicon layer and a gate line is connected to the gate electrode and extends in a direction orthogonally intersecting the fin-shaped silicon layer. A first diffusion layer resides in an upper portion of the pillar-shaped silicon layer and a second diffusion layer resides in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer. A first silicide resides in an upper portion of the first diffusion layer and a second silicide resides in an upper portion of the second diffusion layer. A contact and metal wire are on the second silicide, and a metal wire is on the first contact. | 11-20-2014 |
20140342801 | GAMING MACHINE CAPABLE OF REPEATEDLY EXECUTING A UNIT GAME - A gaming machine that is capable of providing information relevant to a winning combination to a player before spinning of a respective one of reels stops in a unit game is provided. When the player's operation is made, in the case where the predetermined symbol is displayed in the effect reel display region | 11-20-2014 |
20140361383 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of the pillar-shaped silicon layer is equal to a width of the fin-shaped silicon layer. Diffusion layers reside in upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and in a lower portion of the pillar-shaped silicon layer to form. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A contact resides on the metal gate line and a nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of the contact. | 12-11-2014 |
20140374845 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer on a semiconductor substrate and extending in a first direction and a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped silicon layer resides on the fin-shaped silicon layer. A width of the pillar-shaped semiconductor layer, perpendicular to the first direction is equal to a width of the fin-shaped semiconductor layer perpendicular to the first direction. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line extends in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and is connected to the metal gate electrode. A metal gate pad is connected to the metal gate line, where the width of the metal gate electrode and the width of the metal gate pad are larger than the width of the metal gate line. | 12-25-2014 |
20150033714 | HOLDING MATERIAL FOR GAS TREATMENT DEVICE, GAS TREATMENT DEVICE, AND PRODUCTION PROCESSES THEREFOR - Provided are a holding material for a gas treatment device, which is inexpensive, has a simple structure, and exhibits high holding force, a gas treatment device, and a method for manufacturing the same. A holding material for a gas treatment device according to the present invention is a holding material, which is a holding material to be arranged, in a gas treatment device including a treatment structure and a casing for housing the treatment structure, between the treatment structure and the casing, the holding material including silica fibers and an alumina sol in an amount of 3 parts by mass or more in terms of a solid content with respect to 100 parts by mass of the silica fibers. | 02-05-2015 |
20150048443 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pillar-shaped silicon layer and a first-conductivity-type diffusion layer in an upper portion of the pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and polysilicon resides on an upper sidewall of the pillar-shaped silicon layer. A top of the polysilicon of the sidewall is electrically connected to a top of the first-conductivity-type diffusion layer and has the same conductivity as the diffusion layer. | 02-19-2015 |
20150065225 | SLOT MACHINE INCLUDING A PLURALITY OF VIDEO REEL STRIPS - Provided is a slot machine capable of reducing unfairness which may result between a player who has made an investment and a player who has not made an investment and allowing a player to proceed with a game by making an investment in expectation of a jackpot at ease. Each money amount which is constant is accumulated independently of a number of bets each time betting is conducted, and upon winning a jackpot, a money amount calculated by multiplying a money amount accumulated until then by a multiplying factor based on the number of bets is provided. | 03-05-2015 |
20150080105 | GAMING MACHINE - Provided is a gaming machine having new entertainment features, which is achieved by adding new elements in providing a bonus. The gaming machine determines symbols to be rearranged in a display region at random, selects one kind of symbols from a plurality kinds of symbols, places the one kind of symbols in the symbol array associated with at least one of multiple scroll lines, stores symbol arrays in a memory, and scrolls the symbol arrays associated with the scroll lines based on the symbol arrays stored in the memory. | 03-19-2015 |