Patent application number | Description | Published |
20090061606 | METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMPLANT - The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well ( | 03-05-2009 |
20100065823 | GATED RESONANT TUNNELING DIODE - A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer. | 03-18-2010 |
20100093140 | GATED RESONANT TUNNELING DIODE - A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer. | 04-15-2010 |
20110127572 | GATED RESONANT TUNNELING DIODE - A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer. | 06-02-2011 |
20120098590 | QUANTUM ELECTRO-OPTICAL DEVICE USING CMOS TRANSISTOR WITH REVERSE POLARITY DRAIN IMPLANT - A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode. | 04-26-2012 |
20130187252 | BONDPAD INTEGRATED THEROMELECTRIC COOLER - An integrated circuit has thermoelectric cooling devices integrated into bondpads. A method for operating the integrated circuit includes turning a thermal switch to a thermoelectric cooler operate position when the integrated circuit is powered up, turning the thermal switch to a thermoelectric cooler operate position to allow the thermoelectric cooler to operate when the integrated circuit powers down, and turning the thermal switch to a thermoelectric cooler off position when a predetermined integrated circuit chip temperature is reached. | 07-25-2013 |
20130188667 | APPARATUS AND METHOD TO TEST EMBEDDED THERMOELECTRIC DEVICES - An integrated circuit containing an embedded resistor in close proximity to an embedded thermoelectric device. An integrated circuit containing an embedded resistor in close proximity to an embedded thermoelectric device composed of thermoelectric elements and at least one switch to disconnect at least one thermoelectric element from the thermoelectric device. Methods for testing embedded thermoelectric devices. | 07-25-2013 |
20130192655 | THERMOELECTRIC DEVICE EMBEDDED IN A PRINTED CIRCUIT BOARD - A circuit board with an embedded thermoelectric device with hard thermal bonds. A method of embedding a thermoelectric device in a circuit board and forming hard thermal bonds. | 08-01-2013 |
20130255741 | STRUCTURE AND METHOD FOR COUPLING HEAT TO AN EMBEDDED THERMOELECTRIC DEVICE - An integrated circuit with an embedded heat exchanger for coupling heat to an embedded thermoelectric device from a thermal source that is electrically isolated from a thermoelectric device. A method for forming an integrated circuit with an embedded heat exchanger. | 10-03-2013 |