Patent application number | Description | Published |
20120319736 | Comparator and method with adjustable speed and power consumption - A comparator ( | 12-20-2012 |
20130063110 | FAST STARTUP ALGORITHM FOR LOW NOISE POWER MANAGEMENT - A method is provided. A low dropout regulator (LDO) is disabled during a first mode, and a first reference voltage is selected and applied to a switched-mode converter during the first mode. Also during the first mode, a first output voltage is generated by the switched-mode converter from a power supply, and a first capacitor is overcharged with the first output voltage. The LDO is then enabled during a second mode. During a first portion of a startup period for the second mode, a second capacitor is charged from the first capacitor, and a second reference voltage is selected and applied to the switched-mode converter. Then, during a second portion of the startup period for the second mode, the second capacitor is charged with the switched-mode converter. | 03-14-2013 |
20130063111 | POWER MANAGEMENT SYSTEM AND METHOD WITH ADAPTIVE NOISE CONTROL - A method is provided. A first reference voltage during an idle mode is selected, and the first reference voltage is applied to a switched-mode converter. A first output voltage is then generated by the switched-mode converter from a power supply, and a capacitor is overcharged with the first output voltage. The first output voltage is regulated to generate a second output voltage during the idle mode. Then, a second reference voltage during a quiet mode, where the second reference voltage to the buck converter. During the quiet mode, a third output voltage is generated from the switched-mode converter and from discharging the overcharged capacitor, and the third output voltage is regulated to generate the second output voltage. | 03-14-2013 |
20130082671 | Low noise voltage regulator and method with fast settling and low-power consumption - A voltage regulator controls a regulated output voltage (Vout) by feeding it back to a differential input stage ( | 04-04-2013 |
20130082676 | Fast-settling precision voltage follower circuit and method - A voltage follower circuit including an input stage for generating a difference between the input signal and the output signal. An output circuit receiving the first signal and producing the output signal. A slew boost circuit includes a first transistor having a control electrode for receiving the input signal, a first electrode coupled to a first current source, and a second electrode coupled to a first supply voltage, a second transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to the first supply voltage, and a third transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to a second supply voltage. | 04-04-2013 |
20140084994 | Current Limiting Circuitry and Method for Pass Elements and Output Stages - Circuitry ( | 03-27-2014 |
20150054772 | LOW NOISE CAPACITIVE SENSOR WITH INTEGRATED BANDPASS FILTER - A bandpass sense amplifier circuit (FIG. | 02-26-2015 |
20150130755 | Integrated Receiver and ADC for Capacitive Touch Sensing Apparatus and Methods - An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta analog to digital converter configured for direct connection to an analog output of a touch screen device, and further including an integrator circuit having an input coupled for receiving the analog output signal and outputting an integrated output voltage; a comparator coupled to the integrated output voltage and a first bias voltage and outputting a comparison voltage; a clocked sampling latch coupled to the comparison voltage and to a clock signal and outputting quantized data bits corresponding to samples of the comparison voltage; and a digital filter and decimator coupled to the clocked sampling latch and outputting serial data bits which form a digital representation corresponding to the output of the touch screen device. Additional circuits and systems are disclosed. | 05-14-2015 |