Patent application number | Description | Published |
20080224283 | Leadframe-based semiconductor package and fabrication method thereof - A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads. | 09-18-2008 |
20080286938 | Semiconductor device and fabrication methods thereof - A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings. | 11-20-2008 |
20090020864 | Wafer Level package Structure and Fabrication Methods - A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die. | 01-22-2009 |
20090096115 | Semiconductor package and method for fabricating the same - A semiconductor package and a method for fabricating the same are disclosed. The present invention discloses mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interfacial layer or a heat-dissipating member having the interfacial layer on the semiconductor chip, and forming an encapsulant for covering the semiconductor chip, the interfacial layer or the heat dissipating member. The method further includes cutting the encapsulant along edges of the interfacial layer, and removing the redundant encapsulant on the interfacial layer so as to expose the semiconductor chip or the heat-dissipating member without forming burr or heavily wearing cutting tools. | 04-16-2009 |
20090146285 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers, disposing a plurality of electrical connecting points on the chip carriers, performing chip mounting and molding on the chip carrier module to form an encapsulant encapsulating the semiconductor chip, exposing the electrical connecting points from the encapsulant; forming a patterned circuit layer on the encapsulant, electrically connecting the patterned circuit layer to the electrical connecting points, cutting and separating the chip carriers to form a plurality of semiconductor packages each having a circuit layer formed on the encapsulant such that the circuit layer provides extra electrical connecting points and thereby enhances electrical performance of electrical products. During a package stacking process, no package is limited by the design of another package below. | 06-11-2009 |
20100052146 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer. In the present invention, the distance between the semiconductor package and the external device is increased, and thermal stress caused by difference between the thermal expansion coefficients is reduced, so as to enhance the reliability of the product. | 03-04-2010 |
20100151631 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE HAVING HEAT DISSIPATION DEVICE - A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package. | 06-17-2010 |
20100233855 | METHOD FOR FABRICATING CHIP SCALE PACKAGE STRUCTURE WITH METAL PADS EXPOSED FROM AN ENCAPSULANT - A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures. | 09-16-2010 |
20100267202 | METHOD OF FABRICATING STACKED SEMICONDUCTOR STRUCTURE - A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash. | 10-21-2010 |
20100278211 | METHOD AND SYSTEM OF TESTING A SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device, the device includes a substrate, a front-end structure formed in the substrate, a back-end structure formed on the front-end structure, a heater embedded in the back-end structure and operable to generate heat, and a sensor embedded in the back-end structure and operable to sense a temperature of the semiconductor device. | 11-04-2010 |
20110057313 | Enhanced Copper Posts for Wafer Level Chip Scale Packaging - An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint. | 03-10-2011 |
20110070697 | METHOD FOR FABRICATING STACK STRUCTURE OF SEMICONDUCTOR PACKAGES - A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages. | 03-24-2011 |
20110300671 | LEADFRAME-BASED SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads. | 12-08-2011 |
20120119354 | Protecting Flip-Chip Package using Pre-Applied Fillet - A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials. | 05-17-2012 |
20120217632 | Extending Metal Traces in Bump-on-Trace Structures - A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump. | 08-30-2012 |
20120273934 | REDUCED-STRESS BUMP-ON-TRACE (BOT) STRUCTURES - The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased. | 11-01-2012 |
20120306067 | Thermally Enhanced Integrated Circuit Package - According to an embodiment, an integrated circuit package comprises a chip, a thermal component, and a molding compound. The chip comprises an active surface and a backside surface opposite the active surface. The thermal component is physically coupled to the backside surface of the chip. The molding compound encapsulates the chip, and an exposed surface of the thermal component is exposed through the molding compound. Another embodiment is a method to form an integrated circuit package. | 12-06-2012 |
20120319270 | Wafer Level Chip Scale Package with Reduced Stress on Solder Balls - A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus. | 12-20-2012 |
20130001778 | BUMP-ON-TRACE (BOT) STRUCTURES - A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described. | 01-03-2013 |
20130119532 | Bumps for Chip Scale Packaging - A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved. | 05-16-2013 |
20130127040 | DIE CARRIER FOR PACKAGE ON PACKAGE ASSEMBLY - A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package. | 05-23-2013 |
20130127045 | MECHANISMS FOR FORMING FINE-PITCH COPPER BUMP STRUCTURES - The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures. | 05-23-2013 |
20130168855 | Methods and Apparatus for Package On Package Devices with Reduced Strain - Methods and apparatus for package on package structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate, a plurality of package on package connectors extending from a bottom surface and arranged in a pattern of one or more rows proximal to an outer periphery of the first substrate; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface of the second substrate; wherein the pattern of the external connectors is staggered from the pattern of the package on package connectors so that the package on package connectors are not in vertical alignment with the external connectors. Methods for forming structures are disclosed. | 07-04-2013 |
20130175705 | Stress Compensation Layer for 3D Packaging - A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate. | 07-11-2013 |
20130187277 | CRACK STOPPER ON UNDER-BUMP METALLIZATION LAYER - A semiconductor die includes a crack stopper on an under-bump metallization (UBM) layer. The crack stopper is in the shape of hollow cylinder with at least two openings. | 07-25-2013 |
20130221522 | MECHANISMS OF FORMING CONNECTORS FOR PACKAGE ON PACKAGE - The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements. | 08-29-2013 |
20130277828 | Methods and Apparatus for bump-on-trace Chip Packaging - Methods and apparatus for a solder mask trench used in a bump-on-trace (BOT) structure to form a semiconductor package are disclosed. A solder mask layer is formed on a trace and on a substrate. An opening of the solder mask layer, called a solder mask trench, is formed to expose the trace on the substrate. The solder mask trench has a width about a size of a diameter of a solder bump. A solder bump is landed directly on the exposed trace to connect a chip to the trace by an interconnect. With the formation of the solder mask trench, the trace exposed in the solder mask trench have a better grab force, which reduces the trace peeling failure for the semiconductor package. A plurality of solder mask trench rings may be formed in a package. | 10-24-2013 |
20140183746 | Zero Stand-Off Bonding System and Method - A system and method for a zero stand-off configuration are provided. An embodiment comprises forming a seal layer over a conductive region that is part of a first substrate and breaching the seal with a conductive member of a second substrate in order to bond the first substrate to the second substrate. | 07-03-2014 |
20140191394 | Bumps for Chip Scale Packaging - A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved. | 07-10-2014 |
20140203456 | Pre-Applying Supporting Materials between Bonded Package Components - A structure includes a first package component, and a second package component over and bonded to the first package component. A supporting material is disposed in a gap between the first package component and the second package component. A molding material is disposed in the gap and encircling the supporting material. | 07-24-2014 |
20140264810 | Packages with Molding Material Forming Steps - A package includes a first package component having a top surface, a second package component bonded to the top surface of the first package component, and a plurality of electrical connectors at the top surface of the first package component. A molding material is over the first package component and molding the second package component therein. The molding material includes a first portion overlapping the second package component, wherein the first portion includes a first top surface, and a second portion encircling the first portion and molding bottom portions of the plurality of electrical connectors therein. The second portion has a second top surface lower than the first top surface. | 09-18-2014 |
20140264849 | Package-on-Package Structure - A device comprises a bottom package mounted on a printed circuit board, wherein the bottom package comprises a plurality of first bumps formed between the bottom package and the printed circuit board, a first underfill layer formed between the printed circuit board and the bottom package, a semiconductor die mounted on the bottom package and a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps and the top package and the bottom package form a ladder shaped structure. The device further comprises a second underfill layer formed between the bottom package and the top package, wherein the second underfill layer is formed of a same material as the first underfill layer. | 09-18-2014 |