Han, NY
Charles Han, New York, NY US
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20110242126 | CAPTURING IMAGE STRUCTURE DETAIL FROM A FIRST IMAGE AND COLOR FROM A SECOND IMAGE - Embodiments are described for a method to generate an image that includes image structure detail captured from a first image and color from a second image. The first image of a defined subject can be obtained from a computer memory. The first image may be a downsampled fine image with image detail. The second image captured of the defined subject in the first image can be obtained from a computer memory. The second image may be a coarse image. A target pixel in the second image can be selected. A target color distribution for a pixel window of the target pixel can then be computed. A source color distribution for a pixel window of a corresponding pixel in the first image can be computed using a computer processor. Further, a statistic of the target pixel can be determined with respect to the target color distribution. The source color in the source color distribution can be computed with the statistic. The target pixel color can then be replaced by the source color. | 10-06-2011 |
20110243438 | GENERATION OF MULTI-RESOLUTION IMAGE PYRAMIDS - Embodiments are described for a system and method for generating a multi-resolution image pyramid. The method can include obtaining an image captured as a coarse image of a defined subject and a fine image of the defined subject. The fine image can be downsampled to create a temporary image. A further operation is applying a structure transfer operation to the temporary image to transfer color detail from the coarse image. The structure transfer takes place while retaining structural detail from the temporary image. A blending operation can be applied between the temporary image and the fine image to construct an intermediate image for at least one intermediate level in the multi-resolution image pyramid between the fine image and the coarse image. | 10-06-2011 |
Fangfang Han, East Setauket, NY US
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20150379709 | METHOD FOR ADAPTIVE COMPUTER-AIDED DETECTION OF PULMONARY NODULES IN THORACIC COMPUTED TOMOGRAPHY IMAGES USING HIERARCHICAL VECTOR QUANTIZATION AND APPARATUS FOR SAME - Provided are an apparatus and method for fast and adaptive computer-aided detection of pulmonary nodules and differentiation of malignancy from benignancy in thoracic CT images using a hierarchical vector quantization scheme. Anomalous pulmonary nodules are detected by obtaining a two-dimensional (2D) feature model of a pulmonary nodule, segmenting the pulmonary nodule by performing vector quantification to expand the 2D feature model to a three-dimensional (3D) model, and displaying image information representing whether the pulmonary nodule is benign, based upon the 3D model expanded from the 2D feature model, with duplicate information eliminated by performing feature reduction performed using a principal component analysis and a receiver operating characteristics area under the curve merit analysis. A textural feature analysis detects an anomalous pulmonary nodule, and 2D texture features are calculated from 3D volumetric data to provide improved gain compared to calculation from a single slice of 3D data. | 12-31-2015 |
Geng Han, Fishkill, NY US
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20090276736 | Test Pattern Based Process Model Calibration - Embodiments of the present invention provide a method for performing lumped-process model calibration. The method includes creating a plurality of sub-process models for a set of sub-processes; creating a lumped-process-model incorporating said set of sub-processes; calculating a first set of output patterns from a set of test patterns by using said plurality of sub-process models; calculating a second set of output patterns from said set of test patterns by using said lumped-process-model; and adjusting process parameters used in said lumped-process-model to calculate said second set of output patterns to match said first set of output patterns. A computer system for performing the lumped-process model calibration is also provided. | 11-05-2009 |
20090290401 | PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS - A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells. | 11-26-2009 |
20100171031 | CALIBRATION OF LITHOGRAPHIC PROCESS MODELS - A method is provided for calibrating a model of a lithographic process that includes defining a parameter space of lithographic model parameters that are expected in an integrated circuit layout. The parameter space is defined according to bin values of a lithographic model parameter that span the range from a predetermined minimum and maximum value of the model parameter. The bin values may be incremented uniformly between the maximum and minimum parameter values, or may be distributed according to a weighting. The lithographic model is calibrated to an initial calibration test pattern. The resulting simulated calibration pattern is evaluated to determine whether the model parameter space is adequately populated. If the parameter space is over or under populated, the calibration pattern is modified until the calibration pattern test values adequately populate the parameter space, so that the final calibrated lithographic process model will more reliably predict images over the full range of image parameters. | 07-08-2010 |
20110271238 | DECOMPOSITION WITH MULTIPLE EXPOSURES IN A PROCESS WINDOW BASED OPC FLOW USING TOLERANCE BANDS - Setting final dimensions while protecting against the possibility of merging shapes is provided by performing a decomposition of tolerance bands onto a plurality of masks for use in a multi-exposure process. This allows the maximum process latitude between open and short failure mechanisms, while also providing a mechanism to enforce strict CD tolerances in critical regions of a circuit. The decomposition enables co-optimizing various types of shapes placed onto each mask along with the source used to print each mask. Once the tolerance bands are decomposed onto the two or more masks, standard tolerance-band-based data preparation methodologies can be employed to create the final mask shapes. | 11-03-2011 |
20120192137 | PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS - A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells. | 07-26-2012 |
20140282297 | METHOD FOR GENERATING POST-OPC LAYOUT IN CONSIDERATION OF TOP LOSS OF ETCH MASK LAYER - A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer. | 09-18-2014 |
Geng Han, Yorktown Heights, NY US
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20100318956 | METHOD OF INTEGRATED CIRCUIT CHIP FABRICATION AND PROGRAM PRODUCT THEREFOR - A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC. | 12-16-2010 |
George Han, Bronx, NY US
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20120213697 | VERSATILE NANOPARTICULATE BIOMATERIAL FOR CONTROLLED DELIVERY AND/OR CONTAINMENT OF THERAPEUTIC AND DIAGNOSTIC MATERIAL - The invention provides compositions for controlled delivery and/or containment of therapeutic and/or diagnostic agents comprising the agent or agents encapsulated by a matrix containing chitosan, polyethylene glycol (PEG) and/or polyvinyl alcohol (PVA), and tetra-methoxy-ortho-silicate (TMOS) or tetra-ethoxy-ortho-silicate (TEOS), as well as methods for preparing the compositions, and uses of the compositions for therapy and imaging. | 08-23-2012 |
Hanyoung Han, Sunnyside, NY US
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20130034580 | NOVEL FORMULATIONS WHICH STABILIZE AND INHIBIT PRECIPITATION OF IMMUNOGENIC COMPOSITIONS - The present invention addresses an ongoing need in the art to improve the stability of immunogenic compositions such as polysaccharide-protein conjugates and protein immunogens. The invention broadly relates to novel formulations which stabilize and inhibit precipitation of immunogenic compositions. More particularly, the invention described hereinafter, addresses a need in the art for formulations which stabilize and inhibit particulate formation (e.g., aggregation, precipitation) of immunogenic compositions which are processed, developed, formulated, manufactured and/or stored in container means such as fermentors, bioreactors, vials, flasks, bags, syringes, rubber stoppers, tubing and the like. | 02-07-2013 |
Hao Han, Staten Island, NY US
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20160055658 | ITERATIVE RECONSTRUCTION FOR X-RAY COMPUTED TOMOGRAPHY USING PRIOR-IMAGE INDUCED NONLOCAL REGULARIZATION - Disclosed is a method for performing X-ray Computed Tomography scanning, the method including acquiring a plurality of images of an object, obtaining an initial image from the plurality of images, calculating NonLocal weight of the initial image, utilizing a current image estimation and registered prior image, performing a successive over-relaxation optimization to yield a new image estimation with an intensity of the new image estimation equal or greater than zero, performing a cycle update, generating an image of the object utilizing the new image estimation obtained from the optimization, and outputting a resultant image. | 02-25-2016 |
Heather Han, Brooklyn, NY US
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20130261588 | FEMININE HYGIENE PRODUCT - A feminine hygiene product including a tampon, an absorbent pad, and a string connecting the tampon to the absorbent pad is disclosed. The string can include at least one breakable section, or the string may releasably affixed to the absorbent pad. The tampon and/or the absorbent pad can be formed from cotton, rayon, or a cotton-rayon mixture. The feminine hygiene product can further include an applicator sized to accommodate the tampon and the absorbent pad, and to facilitate deployment of the same. | 10-03-2013 |
Hui Han, Ithaca, NY US
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20150177344 | MAGNETIC RESONANCE IMAGING SYSTEMS FOR INTEGRATED PARALLEL RECEPTION, EXCITATION AND SHIMMING AND RELATED METHODS AND DEVICES - Systems, methods and devices are configured for integrated parallel reception, excitation, and shimming (iPRES). Parallel transmit/receive (which can include B?1#191 shimming and/or parallel imaging capabilities) and B | 06-25-2015 |
Hyunjoo Han, Syracuse, NY US
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20120114962 | SYSTEM AND METHOD FOR SYNTHESIZING CORE/ALLOY NANOSTRUCTURES - A system and method to tailor the optical properties of nanomaterials using a core-alloy-shell nano-ultrastructure. Atomic diffusion is used at the nanoscale in order to process as-synthesized nanomaterials into core-alloy-shell architectures. The alloy formation is controlled by the deposition of the alloy solute atoms, and then by alloy interdiffusion of the solute into the core nanoparticle. By controlling temperature, it is possible to control how far the solute diffuses into the core, which in turn allows the tailoring of the optical response of the particle itself. The alloy formation and subsequent interdiffusion allows tailoring of the nanoparticle composition and ultrastructure, resulting in a dramatic tunability of the metal nanostructures surface plasmon response. | 05-10-2012 |
Ja-Hyung Han, Clifton Park, NY US
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20150200111 | PLANARIZATION SCHEME FOR FINFET GATE HEIGHT UNIFORMITY CONTROL - Embodiments of the present invention provide improved methods for fabrication of finFETs. During finFET fabrication, a film, such as amorphous silicon, is deposited on a semiconductor substrate which has regions with fins and regions without fins. A fill layer is deposited on the film and planarized to form a flush surface. A recess or etch process is used to form a planar surface with all portions of the fill layer removed. A finishing process such as a gas cluster ion beam process may be used to further smooth the substrate surface. This results in a film having a very uniform thickness across the structure (e.g. a semiconductor wafer), resulting in improved within-wafer (WiW) uniformity and improved within-chip (WiC) uniformity. | 07-16-2015 |
20150333121 | SHALLOW TRENCH ISOLATION INTEGRATION METHODS AND DEVICES FORMED THEREBY - Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion. | 11-19-2015 |
Jefferson Y. Han, Hollis, NY US
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20160041687 | LOCALIZING AN ELECTROSTATIC STYLUS WITHIN A CAPACITIVE TOUCH SENSOR - Methods, systems, and apparatus relate to capacitive touch sensors with a fine-pointed, active stylus. The active stylus is configured to receive a signal from the capacitive touch sensor for synchronizing a time base of the stylus with the capacitive touch sensor. The active stylus is configured to receive a signal from a matrix of the capacitive touch sensor to measure a first position along one axis, and transmit a signal from the single electrode of the stylus to the matrix to indicate a second position of the stylus along another axis of the matrix. The stylus can transmit the received signal to report the first position of the stylus. | 02-11-2016 |
Jie Han, Niskayuna, NY US
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20130083386 | Optical Imaging System and Method, and Aperture Stop Assembly and Aperture Element - An optical imaging system includes a birefringent element, a light modulating element, and a polarizer element. The birefringent element is configured for decomposing un-polarized light into first linear polarized light and second linear polarized light under different refractive indexes to respectively form a first focal length and a second focal length in the optical imaging system. The light modulating element is configured for modulating a state of polarization of the first and second linear polarized light in response to control signals. The polarizer element is configured for filtering out one of the modulated first and second linear polarized light for creating a single image. | 04-04-2013 |
Jongyoon Han, Ithaca, NY US
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20090047681 | ENTROPIC TRAPPING AND SIEVING OF MOLECULES - Nanofluidic entropic traps, comprising alternating thin and thick regions, sieve small molecules such as DNA or protein polymers and other molecules. The thick region is comparable or substantially larger than the molecule to be separated, while the thin region is substantially smaller than the size of the molecules to be separated. Due to the molecular size dependence of the entropic trapping effect, separation of molecules may be achieved. In addition, entropic traps are used to collect, trap and control many molecules in the nanofluidic channel. A fabrication method is disclosed to provide an efficient way to make nanofluidic constrictions in any fluidic devices. | 02-19-2009 |
Keesook Han, Rome, NY US
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20150200962 | METHOD AND SYSTEM FOR RESILIENT AND ADAPTIVE DETECTION OF MALICIOUS WEBSITES - A computer-implemented method for detecting malicious websites includes collecting data from a website. The collected data includes application-layer data of a URL, wherein the application-layer data is in the form of feature vectors; and network-layer data of a URL, wherein the network-layer data is in the form of feature vectors. Determining if a website is malicious based on the collected application-layer data vectors and the collected network-layer data vectors. | 07-16-2015 |
Kyusang Han, Port Washington, NY US
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20120260516 | ROTATING AIR DIRECTING APPARATUS FOR A HAIR DRYER - A rotating air directing apparatus for a hair dryer is provided. The apparatus includes a tubular rotating member and a nozzle member disposed adjacent to an outlet opening of the tubular rotating member and adapted to rotate with the tubular rotating member. The nozzle member includes an angled tubular member having a nozzle opening disposed at an acute angle relative to the outlet opening. A plurality of curved vanes each have a fixed edge at a circumferential inner surface of the tubular rotating member, and an opposing free edge that defines a central open space of the tubular rotating member. Each of the plurality of curved vanes are spaced apart from each other, thereby defining a plurality of curved radial openings between adjacent curved vanes. | 10-18-2012 |
20130014402 | ROTATING AIR DIRECTING APPARATUS FOR A HAIR DRYER - A rotating air directing apparatus for a barrel of a hair dryer is provided. The apparatus includes a tubular adapter member having an inlet opening and an outlet opening. The inlet opening is adapted to be removably coupled to the barrel of the hair dryer. The apparatus also includes a propeller member rotatably coupled to the tubular adapter member. The propeller member includes a plurality of curved vanes extending from a central cylinder. The apparatus further includes a nozzle member disposed adjacent to the outlet opening of the tubular adapter member and adapted to rotate with the propeller member. The nozzle member includes an angled tubular member having a nozzle opening disposed at an acute angle relative to the outlet opening of the tubular adapter member. | 01-17-2013 |
20130104415 | ROTATING AIR DIRECTING APPARATUS FOR A HAIR DRYER | 05-02-2013 |
20130247934 | HAIR STRAIGHTENING APPARATUS - A hair straightening apparatus is provided. The hair straightening apparatus includes an upper clamping member and a lower clamping member attached to the upper clamping member at a hinge. A lower heating element extends from the lower clamping member. The lower heating element also includes a top heating surface and an opposing bottom heating surface. | 09-26-2013 |
20140090657 | ARTIFICIAL NAIL OR TIP ARRANGEMENT AND METHOD OF MAKING SAME - An artificial nail or tip arrangement and method of making the same are provided. The arrangement includes at least one body having a concave lower surface with a shape corresponding to a natural nail. The arrangement also includes an adhesive layer having a first surface and an opposing second surface. The first surface adheres to the concave lower surface of the at least one body and the second surface is provided to adhere to the natural nail when applied thereto. The arrangement further includes a removable layer that covers the second surface of the adhesive layer, and which is removable to expose the second surface of the adhesive layer for application to the natural nail. The removable layer is provided with a one or more slits so that a surface of the removable layer remains smooth after adherence of the first surface of the adhesive layer with the concave lower surface of the at least one body. | 04-03-2014 |
Kyu Sang Han, Port Washington, NY US
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20080251092 | Artificial nail and method of forming same - An artificial nail is formed by injection molding a first section and a second section. The first section and second section are adjacent to one another. One of the sections defines a front distal tip of the artificial nail and is formed by injecting a quantity of heated material under pressure from a nozzle into a sprue, through a runner and through a cavity gate into a mold cavity. The other section is formed by injecting another quantity of heated material under pressure from a heated nozzle through another cavity gate into the mold cavity. | 10-16-2008 |
20110030711 | Artificial nail and method of forming same - An injection molded artificial nail is formed by forming a first section using a runner system method, forming a second section using a runner system method and forming a third section by a hot tip gate process. The second and third sections are disposed under the first section. The second section has a second section end and the third section has a third section end adjoining the second section end. The first section forms a top surface of the artificial nail extending from a front distal tip of the artificial nail to a back proximal end of the artificial nail and completely covers the second section and the third section. | 02-10-2011 |
20110073124 | Ultrasonic artificial nail remover with a natural nail shaped tip - An ultrasonic wave energy artificial nail remover in one aspect includes a handle, a body attached to the handle, an ultrasonic sound wave generator attached to the body, and a tip having the shape of a natural nail. The tip is made to vibrate by the ultrasonic sound wave generator. The shape of the tip allows for a quicker removal of the artificial nail and requires less skill to successfully remove an artificial nail without damaging the natural nail than removal with a narrow flat tip allows and requires. Ultrasonic energy is channeled through the natural nail shaped tip to facilitate removal of an artificial nail in a quick manner with little cleanup involved. | 03-31-2011 |
20110079236 | Artificial eyelash and method for applying same - An artificial eyelash assembly includes a base strand having a first end and a second end opposite the first end and a plurality of hairs. A first loop is disposed proximate the first end of the base strand and a second loop is disposed proximate the second end of the base strand. A first flexible member is coupled to the first loop and a second flexible member is coupled to the second loop. | 04-07-2011 |
20110132384 | ARTIFICIAL NAIL OR TIP ARRANGEMENT AND METHOD OF MAKING SAME - Exemplary embodiments of artificial nail or tip arrangement and method of making the same can be provided. For example, at least one body can be provided which can have a particular surface with a shape that at least approximately corresponds to a shape of at least one portion of a natural nail. Further, an adhesive layer can be secured to at least one portion of the surface of the body. The adhesive layer can have a first surface which adheres to at least one portion of the particular surface of the body and a second surface which is provided to adhere to an upper surface of the at least one portion of the natural nail when directly applied thereto. Further, a removable layer can be provided which covers at least one section of the second surface of the adhesive layer, and which is removable to expose at least one portion of the second surface of the adhesive layer for an application to the upper surface of the portion of the natural nail. The removable layer can include at least one section which extends outwardly outside a periphery of the body. | 06-09-2011 |
20130160783 | APPARATUS FOR APPLYING AN ARTIFICIAL EYELASH - An apparatus is provided for applying artificial eyelashes. The apparatus includes a main body, upon which an artificial eyelash is disposed. The main body has a length extending in a single plane. The apparatus also includes one or more legs extending from the main body. At least one of the one or more legs is angled away from the single plane of the main body. | 06-27-2013 |
20130160787 | APPARATUS FOR PACKAGING AND APPLYING AN ARTIFICIAL EYELASH AND METHOD FOR APPLYING THE PACKAGED ARTIFICIAL EYELASH - An apparatus is provided for packaging and applying artificial eyelashes, and a method is provided for applying the packaged artificial eyelashes. The apparatus includes a packaging tray having a top surface, and at least one artificial eyelash applicator integrated with the top surface of the packaging tray through at least one attachment point, and removable from the packaging tray when the at least one attachment point is broken. | 06-27-2013 |
20150216246 | APPLICATORS FOR ARTIFICIAL EYELASHES AND KITS FOR APPLYING ARTIFICIAL EYELASHES - The present disclosure relates to an applicator for artificial eyelashes and a kit for applying artificial eyelashes. The applicator includes a first leg, a second leg rotatably coupled to the first leg at a hinge joint, a first body portion connected to the first leg, and a second body portion connected to the second leg. The first body portion includes a first flange positioned opposite the hinge joint, and the second body portion includes a second flange positioned opposite the hinge joint. The first flange matingly receives the second flange when the second leg is rotated toward the first leg. | 08-06-2015 |
20160029767 | Fingernail Coverings and Related Systems and Methods - In some aspects, fingernail coverings can include a flexible sheet layer configured to conform to and cover at least a portion a fingernail, the flexible sheet layer defining a first surface configured to adhere to the portion of the fingernail, and a fingernail tip extension disposed along an end region of the flexible sheet layer, the fingernail tip extension being arranged to expose an area of a second surface of the flexible sheet layer to be installed over a proximal end of the fingernail. | 02-04-2016 |
Margaret Han, Water Mill, NY US
Melinda Y. Han, New York, NY US
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20090140801 | Locally gated graphene nanostructures and methods of making and using - A locally gated graphene nanostructure is described, along with methods of making and using the same. A graphene layer can include first and second terminal regions separated by a substantially single layer gated graphene nanoconstriction. A local first gate region can be separated from the graphene nanoconstriction by a first gate dielectric. The local first gate region can be capacitively coupled to gate electrical conduction in the graphene nanoconstriction. A second gate region can be separated from the graphene nanoconstriction by a second gate dielectric. The second gate region can be capacitively coupled to provide a bias to a first location in the graphene nanoconstriction and to a second location outside of the graphene nanoconstriction. Methods of making and using locally gated graphene nanostructures are also described. | 06-04-2009 |
20140183736 | GRAPHENE ELECTRODES FOR ELECTRONIC DEVICES - A laminated graphene device is demonstrated as a cathode. In one example the devices include organic photovoltaic devices. The measured properties demonstrate work-function matching via contact doping. Devices and method shown also provide increased power conversion efficiency due to transparency. These findings indicate that flexible, light-weight all carbon devices, such as solar cells, can be constructed using graphene as the cathode material. | 07-03-2014 |
Pengyu Han, Troy, NY US
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20110036984 | TUNABLE BROADBAND ANTI-RELFECTION APPARATUS - A broadband anti-reflection apparatus for use with terahertz radiation includes a layer having an outer surface comprising a plurality of pyramid structures having about a 30 μm to about a 110 μm period, and wherein reflectance of the terahertz radiation is reduced compared to a layer comprising a planar outer surface. Also disclosed is a method for modifying terahertz radiation which includes receiving terahertz radiation on a device having an anti-reflection layer having an outer surface comprising a plurality of pyramid structures having about a 30 μm to a 110 μm period, and modifying the terahertz radiation passing through the device or processing the terahertz radiation in the device. | 02-17-2011 |
Ruonan Han, Ithaca, NY US
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20150288393 | System and Method for Signal Generation - A high-power broadband radiation system and method are disclosed. The system includes an array of harmonic oscillators with mutual coupling through quadrature oscillators. Based on a self-feeding structure, the presently disclosed harmonic oscillators simultaneously achieve optimum conditions for fundamental oscillation and 2nd-harmonic generation. The signals at the second harmonic radiate through on-chip slot antennas, and are in-phase combined inside a hemispheric silicon lens attached at the backside of the chip. In some embodiments, the radiation of the system can also be modulated by narrow pulses generated on chip, thereby achieving broad radiation bandwidth. | 10-08-2015 |
Sang Cheol Han, Clifton Park, NY US
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20150333121 | SHALLOW TRENCH ISOLATION INTEGRATION METHODS AND DEVICES FORMED THEREBY - Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion. | 11-19-2015 |
Shu-Jen Han, Cortlandt Manor, NY US
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20110223612 | Magnetic Sensor Based Quantitative Binding Kinetics Analysis - Methods for quantitatively determining a binding kinetic parameter of a molecular binding interaction are provided. Aspects of embodiments of the methods include: producing a magnetic sensor device including a magnetic sensor in contact with an assay mixture including a magnetically labeled molecule to produce a detectable molecular binding interaction; obtaining a real-time signal from the magnetic sensor; and quantitatively determining a binding kinetics parameter of the molecular binding interaction from the real-time signal. Also provided are systems and kits configured for use in the methods. | 09-15-2011 |
20110227043 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 09-22-2011 |
20110315961 | Ultrathin Spacer Formation for Carbon-Based FET - A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET. | 12-29-2011 |
20120007054 | Self-Aligned Contacts in Carbon Devices - A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity. | 01-12-2012 |
20120043585 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 02-23-2012 |
20120132913 | III-V Compound Semiconductor Material Passivation With Crystalline Interlayer - The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure. | 05-31-2012 |
20120146001 | ULTRATHIN SPACER FORMATION FOR CARBON-BASED FET - A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer. | 06-14-2012 |
20120175594 | Graphene Devices with Local Dual Gates - An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer. | 07-12-2012 |
20120187505 | Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed. | 07-26-2012 |
20120248509 | STRUCTURE AND PROCESS FOR METAL FILL IN REPLACEMENT METAL GATE INTEGRATION - Processes for metal fill in replacement metal gate integration schemes and resultant devices are provided herein. The method includes forming a dummy gate on a semiconductor substrate. The dummy gate includes forming a metal layer between a first material and a second material. The method further includes partially removing the dummy gate to form an opening bounded by a spacer material. The method further includes forming a recess in the spacer material to widen a portion of the opening. The method further includes removing a remaining portion of the dummy gate through the opening to form a trench having the recess forming an upper portion thereof. The method further includes filling the trench and the recess with a replacement metal gate stack. | 10-04-2012 |
20120248535 | SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET) AND INTEGRATED CIRCUIT (IC) CHIP - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer. | 10-04-2012 |
20120280279 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 11-08-2012 |
20120292597 | Self-Aligned Contacts in Carbon Devices - A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity. | 11-22-2012 |
20120292602 | SELF-ALIGNED CARBON ELECTRONICS WITH EMBEDDED GATE ELECTRODE - A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack comprising a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions. | 11-22-2012 |
20120306026 | REPLACEMENT GATE ELECTRODE WITH A TUNGSTEN DIFFUSION BARRIER LAYER - A tungsten barrier portion is employed in a replacement gate structure to block diffusion of material from a metal portion to a work function material portion. The tungsten barrier portion effectively functions as a diffusion barrier layer between the metal portion and the work function material portion so that the composition of the work function material portion is unaffected by anneal and/or usage of the field effect transistor including the replacement gate structure. Thus, the threshold voltage of the field effect transistor can remain stable throughout processing steps and usage in the field. | 12-06-2012 |
20120326126 | Graphene or Carbon Nanotube Devices with Localized Bottom Gates and Gate Dielectric - Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device. | 12-27-2012 |
20120326228 | SELF-ALIGNED CARBON ELECTRONICS WITH EMBEDDED GATE ELECTRODE - A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack comprising a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions. | 12-27-2012 |
20120329193 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 12-27-2012 |
20130001519 | GRAPHENE DEVICES WITH LOCAL DUAL GATES - An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer. | 01-03-2013 |
20130020658 | REPLACEMENT GATE ELECTRODE WITH PLANAR WORK FUNCTION MATERIAL LAYERS - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 01-24-2013 |
20130082242 | TRANSISTOR DEVICE WITH REDUCED GATE RESISTANCE - A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided. | 04-04-2013 |
20130087759 | Light Emitting Diode (LED) Using Carbon Materials - Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material. | 04-11-2013 |
20130093000 | VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE - A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate. | 04-18-2013 |
20130093018 | CARBON IMPLANT FOR WORKFUNCTION ADJUSTMENT IN REPLACEMENT GATE TRANSISTOR - A method includes providing a wafer that has a semiconductor layer having an insulator layer disposed on the semiconductor layer. The insulator layer has openings made therein to expose a surface of the semiconductor layer, where each opening corresponds to a location of what will become a transistor channel in the semiconductor layer disposed beneath a gate stack. The method further includes depositing a high dielectric constant gate insulator layer so as to cover the exposed surface of the semiconductor layer and sidewalls of the insulator layer; depositing a gate metal layer that overlies the high dielectric constant gate insulator layer; and implanting Carbon through the gate metal layer and the underlying high dielectric constant gate insulator layer so as to form in an upper portion of the semiconductor layer a Carbon-implanted region having a concentration of Carbon selected to establish a voltage threshold of the transistor. | 04-18-2013 |
20130093021 | CARBON IMPLANT FOR WORKFUNCTION ADJUSTMENT IN REPLACEMENT GATE TRANSISTOR - A transistor includes a semiconductor body having a channel formed in the semiconductor body; a high dielectric constant gate insulator layer disposed over a surface of an upper portion of the channel; and a gate metal layer disposed over the high dielectric constant gate insulator layer. The channel contains Carbon implanted through the gate metal layer, the high dielectric constant gate insulator layer and the surface to form in the upper portion of the channel a Carbon-implanted region having a substantially uniform concentration of Carbon selected to establish a voltage threshold of the transistor. | 04-18-2013 |
20130095623 | VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE - A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate. | 04-18-2013 |
20130113081 | QUANTUM CAPACITANCE GRAPHENE VARACTORS AND FABRICATION METHODS - A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included. | 05-09-2013 |
20130126830 | TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES - A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel. | 05-23-2013 |
20130130446 | TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES - A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel. | 05-23-2013 |
20130143769 | Graphene Nanomesh Based Charge Sensor - A graphene nanomesh based charge sensor and method for producing a graphene nanomesh based charge sensor. The method includes generating multiple holes in graphene in a periodic way to create a graphene nanomesh with a patterned array of multiple holes, passivating an edge of each of the multiple holes of the graphene nanomesh to allow for functionalization of the graphene nanomesh, and functionalizing the passivated edge of each of the multiple holes of the graphene nanomesh with a chemical compound that facilitates chemical binding of a receptor of a target molecule to the edge of one or more of the multiple holes, allowing the target molecule to bind to the receptor, causing a charge to be transferred to the graphene nanomesh to produce a graphene nanomesh based charge sensor for the target molecule. | 06-06-2013 |
20130153964 | FETs with Hybrid Channel Materials - Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET. | 06-20-2013 |
20130168834 | III-V COMPOUND SEMICONDUCTOR MATERIAL PASSIVATION WITH CRYSTALLINE INTERLAYER - The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure. | 07-04-2013 |
20130234762 | CIRCUIT INCLUDING A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE HAVING A GRAPHENE CHANNEL, AND METHOD OF OPERATING THE CIRUCIT - A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance. | 09-12-2013 |
20130244386 | SELF-ALIGNED CARBON ELECTRONICS WITH EMBEDDED GATE ELECTRODE - A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions. | 09-19-2013 |
20130248823 | SEMICONDUCTOR DEVICE INCLUDING GRAPHENE LAYER AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, first plural contacts formed in the substrate, a graphene layer formed on the substrate and on the first plural contacts and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts. | 09-26-2013 |
20130307089 | Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy And Contact Formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed. | 11-21-2013 |
20130309830 | Self-Aligned III-V MOSFET Fabrication with In-Situ III-V Epitaxy And In-Situ Metal Epitaxy And Contact Formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed. | 11-21-2013 |
20130328016 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 12-12-2013 |
20130328017 | SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS - A graphene-based electrically tunable nanoconstriction device and a non-transitory tangible computer readable medium encoded with a program for fabricating the device that includes a back-gate dielectric layer over a conductive substrate are described. The back-gate dielectric layer may be hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts formed over a portion of the graphene layer include at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between at least one source contact, at least one the drain contact and at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer. | 12-12-2013 |
20130330885 | SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS - A method to fabricate a novel graphene based, electrically tunable, nanoconstriction device is described. The device includes a back-gate dielectric layer formed over a conductive substrate. The back-gate dielectric layer is, in one example, hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts are formed over a portion of the graphene layer including at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between the at least one source contact, the at least one the drain contact and the at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer. | 12-12-2013 |
20130337618 | TRANSISTOR DEVICE WITH REDUCED GATE RESISTANCE - A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided. | 12-19-2013 |
20140001542 | PASSIVATION OF CARBON NANOTUBES WITH MOLECULAR LAYERS | 01-02-2014 |
20140004666 | PASSIVATION OF CARBON NANOTUBES WITH MOLECULAR LAYERS | 01-02-2014 |
20140042385 | CONTACTS-FIRST SELF-ALIGNED CARBON NANOTUBE TRANSISTOR WITH GATE-ALL-AROUND - A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed. | 02-13-2014 |
20140042561 | REPLACEMENT GATE ELECTRODE WITH PLANAR WORK FUNCTION MATERIAL LAYERS - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 02-13-2014 |
20140045303 | CONTACTS-FIRST SELF-ALIGNED CARBON NANOTUBE TRANSISTOR WITH GATE-ALL-AROUND - A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed. | 02-13-2014 |
20140070284 | SELF-ALIGNED CARBON NANOSTRUCTURE FIELD EFFECT TRANSISTORS USING SELECTIVE DIELECTRIC DEPOSITION - Self-aligned carbon nanostructure field effect transistor structures are provided, which are formed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer. | 03-13-2014 |
20140073093 | SELF-ALIGNED CARBON NANOSTRUCTURE FIELD EFFECT TRANSISTORS USING SELECTIVE DIELECTRIC DEPOSITION - Self-aligned carbon nanostructure field effect transistor structures are provided, which are foamed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer. | 03-13-2014 |
20140076721 | ELECTROCHEMICAL ETCHING APPARATUS - An electroplating etching apparatus includes a power to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode. | 03-20-2014 |
20140076738 | ELECTROCHEMICAL ETCHING APPARATUS - An electroplating etching apparatus includes a power supply to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode. | 03-20-2014 |
20140151642 | 3D RFICS WITH ULTRA-THIN SEMICONDUCTOR MATERIALS - Three-dimensional integrated circuits include an active layer having one or more active components formed with carbon-based channel material; a passive layer monolithically formed with the active layer, having one or more sub-layers and each sub-layer having one or more passive components, where the passive components have monolithically formed vertical interconnects to components on other layers; and a surface layer monolithically formed with the passive layer, including one or more surface components connected to one or more of the passive components through monolithically formed vias. | 06-05-2014 |
20140151786 | NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH - Non-volatile switches and methods for making the same include a gate material formed in a recess of a substrate; a flexible conductive element disposed above the gate material, separated from the gate material by a gap, where the flexible conductive element is supported on at least two points across the gap, and where a voltage above a gate threshold voltage causes a deformation in the flexible conductive element such that the flexible conductive element comes into contact with a drain in the substrate, thereby closing a circuit between the drain and a source terminal. The gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening the circuit. | 06-05-2014 |
20140151847 | AREA-EFFICIENT CAPACITOR USING CARBON NANOTUBES - An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating. | 06-05-2014 |
20140154851 | NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH - Methods for making non-volatile switches include depositing gate material in a recess of a substrate; depositing drain metal in a recess of the gate material; planarizing the gate material, drain metal, and substrate; forming sidewalls by depositing material on the substrate around the gate material; forming a flexible conductive element between the sidewalls to establish a gap between the flexible conductive element and the gate material, such that the gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening a circuit; and forming a source terminal in electrical contact with the flexible conductive element. | 06-05-2014 |
20140154858 | AREA-EFFICIENT CAPACITOR USING CARBON NANOTUBES - An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating. | 06-05-2014 |
20140158551 | CARBON BASED BIOSENSORS AND PROCESSES OF MANUFACTURING THE SAME - Sensors, processes for manufacturing the sensors, and processes of detecting a target molecule with the sensor generally includes a substrate including a channel and first and second electrodes electrically connected to the channel, wherein the channel includes a monolayer of surface functionalized graphene or surface functionalized carbon nanotubes, wherein the surface functionalized graphene or surface functionalized carbon nanotubes include an imidazolidone compound. | 06-12-2014 |
20140162375 | CARBON BASED BIOSENSORS AND PROCESSES OF MANUFACTURING THE SAME - Sensors, processes for manufacturing the sensors, and processes of detecting a target molecule with the sensor generally includes a substrate including a channel and first and second electrodes electrically connected to the channel, wherein the channel includes a monolayer of surface functionalized graphene or surface functionalized carbon nanotubes, wherein the surface functionalized graphene or surface functionalized carbon nanotubes include an imidazolidone compound. | 06-12-2014 |
20140162390 | CARBON BASED BIOSENSORS AND PROCESSES OF MANUFACTURING THE SAME - Sensors, processes for manufacturing the sensors, and processes of detecting a target molecule with the sensor generally includes a substrate including a channel and first and second electrodes electrically connected to the channel, wherein the channel includes a monolayer of surface functionalized graphene or surface functionalized carbon nanotubes, wherein the surface functionalized graphene or surface functionalized carbon nanotubes include an imidazolidone compound. | 06-12-2014 |
20140217481 | PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE - A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack. | 08-07-2014 |
20140312412 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer. | 10-23-2014 |
20140312413 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions a gate structure embedded in a substrate; self-aligned source and drain contacts embedded in the substrate around the gate structure; and a channel layer over the gate structure and self-aligned source and drain contacts. The source and drain contacts extend above the channel layer. | 10-23-2014 |
20140326604 | INTEGRATED NANOWIRE/NANOSHEET NANOGAP AND NANOPORE FOR DNA AND RNA SEQUENCING - A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current. | 11-06-2014 |
20140326954 | INTEGRATED NANOWIRE/NANOSHEET NANOGAP AND NANOPORE FOR DNA AND RNA SEQUENCING - A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current. | 11-06-2014 |
20140332851 | REDUCED SHORT CHANNEL EFFECT OF III-V FIELD EFFECT TRANSISTOR VIA OXIDIZING ALUMINUM-RICH UNDERLAYER - In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region. | 11-13-2014 |
20140332855 | REDUCED SHORT CHANNEL EFFECT OF III-V FIELD EFFECT TRANSISTOR VIA OXIDIZING ALUMINUM-RICH UNDERLAYER - In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region. | 11-13-2014 |
20140332860 | STACKED CARBON-BASED FETS - Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower channel material, each pair separated by an insulator; forming an upper channel material over the source regions, drain regions, and gate regions; and providing electrical access to the source, drain, and gate regions. | 11-13-2014 |
20140332862 | STACKED CARBON-BASED FETS - Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions. | 11-13-2014 |
20150060770 | Light Emitting Diode (LED) Using Carbon Materials - Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material. | 03-05-2015 |
20150137078 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 05-21-2015 |
20150187764 | STACKED CARBON-BASED FETS - A stacked transistor device includes a lower transistor that has a lower channel layer formed on a substrate and lower source and drain regions formed directly over the lower channel layer. The lower source and drain regions are in electrical contact with respective conductive source and drain extensions formed in the substrate. An upper transistor has upper source and drain regions vertically aligned with the respective lower source and drain regions. The upper source and drain regions are separated from the respective lower source and drain regions by an insulator. The upper transistor further includes an upper channel layer formed over the upper source and drain regions. | 07-02-2015 |
20150187897 | PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE - A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack. | 07-02-2015 |
20150191842 | ELECTROCHEMICAL ETCHING APPARATUS - An electroplating etching apparatus includes a power to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode. | 07-09-2015 |
20150194536 | GRAPHENE DEVICES WITH LOCAL DUAL GATES - An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer. | 07-09-2015 |
20150194619 | SEMICONDUCTOR DEVICE WITH BALLISTIC GATE LENGTH STRUCTURE - Embodiments of the invention include a method of fabrication and a semiconductor structure. The method of fabrication includes depositing a first dielectric material on a substrate, and forming a bottom gate comprising filling a first opening in the first dielectric layer with a first conductive material. Next, depositing a second dielectric material, and forming a trench in the second dielectric material down to the first conductive material. Next, depositing a second conductive material on the sidewall of the trench forming an electrical connection between the first conductive material and the second conductive material, depositing a third dielectric material in the trench, and removing excess material not in the trench. Next, depositing a gate dielectric layer, and forming a channel layer of carbon nanotubes on the gate dielectric layer. Lastly, depositing a third conductive material on the channel layer forming source and drain terminals. | 07-09-2015 |
20150221884 | CARBON NANOTUBE TRANSISTOR HAVING EXTENDED CONTACTS - A semiconductor device includes a substrate that extends along a first direction to define a length and second direction perpendicular to the first direction to define a height. The substrate includes a dielectric layer and at least one gate stack formed on the dielectric layer. A source contact is formed adjacent to a first side of the gate stack and a drain contact formed adjacent to an opposing second side of the gate stack. A carbon nanotube is formed on the source contact and the drain contact. A first portion of the nanotube forms a source. A second portion forms a drain. A third portion is interposed between the source and drain to define a gate channel that extends along the first direction. The source and the drain extend along the second direction and have a greater length than the gate channel. | 08-06-2015 |
20150228753 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses. The source and drain contacts extend above the channel layer. | 08-13-2015 |
20150233900 | Graphene Nanomesh Based Charge Sensor - A graphene nanomesh based charge sensor and method for producing a graphene nanomesh based charge sensor. The method includes generating multiple holes in graphene to create a graphene nanomesh with a patterned array of multiple holes; passivating an edge of each of the multiple holes of the graphene nanomesh to allow for functionalization of the graphene nanomesh; and functionalizing the passivated edge of each of the multiple holes of the graphene nanomesh with a chemical compound that facilitates chemical binding of a receptor of a target molecule to the edge of one or more of the multiple holes, wherein the receptor is a molecule that chemically binds to the target molecule, irrespective of the size of the target molecule. | 08-20-2015 |
20150235903 | Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy and Contact Formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed. | 08-20-2015 |
20150255631 | QUANTUM CAPACITANCE GRAPHENE VARACTORS AND FABRICATION METHODS - A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included. | 09-10-2015 |
20150267317 | ELECTROCHEMICAL ETCHING APPARATUS - An electroplating etching apparatus includes a power to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode. | 09-24-2015 |
20150276726 | Graphene Nanomesh Based Charge Sensor - A graphene nanomesh based charge sensor and method for producing a graphene nanomesh based charge sensor. A graphene nanomesh based charge sensor includes a graphene nanomesh with a patterned array of multiple holes created by generating multiple holes in graphene in a periodic way, wherein: an edge of each of the multiple holes of the graphene nanomesh is passivated; and the passivated edge of each of the multiple holes of the graphene nanomesh is functionalized with a chemical compound that facilitates chemical binding of a receptor of a target molecule to the edge of one or more of the multiple holes, allowing the target molecule to bind to the receptor, causing a charge to be transferred to the graphene nanomesh to produce a graphene nanomesh based charge sensor for the target molecule. | 10-01-2015 |
20150287942 | FORMING PN JUNCTION CONTACTS BY DIFFERENT DIELECTRICS - A carbon nanotube transistor and method of manufacturing a carbon nanotube transistor is disclosed. The carbon nanotube transistor includes a carbon nanotube on a substrate, a gate electrode deposited on the carbon nanotube, and at least one of a source electrode and a drain electrode deposited on the carbon nanotube and separated from the gate electrode by a space region. The carbon nanotube is doped at the gate electrode an in the space region to form a p-n junction. | 10-08-2015 |
20160087232 | SEMICONDUCTOR DEVICE WITH BALLISTIC GATE LENGTH STRUCTURE - Embodiments of the invention include a method of fabrication of a semiconductor structure. The method of fabrication includes: Forming a trench in a first dielectric material down to a first conductive material of a bottom gate. A sidewall of the trench contacts a top surface of the first conductive material. Depositing a second conductive material on the sidewall of the trench, which forms an electrical connection with the first conductive material. Depositing a second dielectric material a in the trench, and on the second conductive material. Depositing a gate dielectric material on the second conductive material and the dielectric materials. Forming a channel material on the gate dielectric material. Depositing another conductive material on the channel material and portions of the gate dielectric material to form a source terminal and a drain terminal. | 03-24-2016 |
20160093819 | FRINGING FIELD ASSISTED DIELECTROPHORESIS ASSEMBLY OF CARBON NANOTUBES - A method of arranging at least one carbon nanotube on a semiconductor substrate includes depositing the at least one carbon nanotube on a dielectric layer of the semiconductor device. The method further includes arranging the at least one carbon nanotube on the dielectric layer in response to applying a voltage potential to an electrically conductive electrode of the semiconductor device, and applying a ground potential to an electrically conductive semiconductor layer of the semiconductor device. | 03-31-2016 |
20160099332 | PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE - A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack. | 04-07-2016 |
Shu-Jen Han, Wappingers Falls, NY US
Patent application number | Description | Published |
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20100276753 | Threshold Voltage Adjustment Through Gate Dielectric Stack Modification - Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration. | 11-04-2010 |
20110049624 | MOSFET ON SILICON-ON-INSULATOR REDX WITH ASYMMETRIC SOURCE-DRAIN CONTACTS - A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region. | 03-03-2011 |
20110215300 | GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices. | 09-08-2011 |
20110241120 | Field Effect Transistor Device and Fabrication - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 10-06-2011 |
20110248362 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 10-13-2011 |
20120007183 | Multi-gate Transistor Having Sidewall Contacts - A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer. | 01-12-2012 |
20120032149 | Vertical Stacking of Carbon Nanotube Arrays for Current Enhancement and Control - Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided. | 02-09-2012 |
20120108017 | THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION - Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration. | 05-03-2012 |
20120286366 | Field Effect Transistor Device and Fabrication - In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET. | 11-15-2012 |
20120295423 | GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices. | 11-22-2012 |
20120299125 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 11-29-2012 |
20120326236 | MULTI-GATE TRANSISTOR HAVING SIDEWALL CONTACTS - A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer. | 12-27-2012 |
20130015428 | Vertical Stacking of Carbon Nanotube Arrays for Current Enhancement and Control - Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided. | 01-17-2013 |
20130171813 | FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 07-04-2013 |
20130230978 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 09-05-2013 |
Shu-Jen Han, Yorktown Heights, NY US
Patent application number | Description | Published |
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20110115044 | DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE - A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other. | 05-19-2011 |
20120112310 | DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE - A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other. | 05-10-2012 |
Shu-Jen Han, Hopewell Junction, NY US
Patent application number | Description | Published |
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20110121370 | EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES - A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material. | 05-26-2011 |
20120261728 | EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES - A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape. | 10-18-2012 |
Shu-Jen Han, Cortland Manor, NY US
Patent application number | Description | Published |
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20120286244 | CARBON FIELD EFFECT TRANSISTORS HAVING CHARGED MONOLAYERS TO REDUCE PARASITIC RESISTANCE - Carbon transistor devices having channels formed from carbon nanostructures, such as carbon nanotubes or graphene, and having charged monolayers to reduce parasitic resistance in un-gated regions of the channels, and methods for fabricating carbon transistor devices having charged monolayers to reduce parasitic resistance. For example, a carbon field effect transistor includes a channel comprising a carbon nanostructure formed on an insulating layer, a gate structure formed on the channel, a monolayer of DNA conformally covering the gate structure and a portion of the channel adjacent the gate structure, an insulating spacer conformally formed on the monolayer of DNA, and source and drain contacts connected by the channel | 11-15-2012 |
20130082243 | TRANSISTOR DEVICE WITH REDUCED GATE RESISTANCE - A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided. | 04-04-2013 |
20140151641 | 3D RFICS WITH ULTRA-THIN SEMICONDUCTOR MATERIALS - Three-dimensional integrated circuits and method for fabricating the same include forming one or more passive components in a passive-layer dielectric; depositing additional dielectric material on the passive-layer dielectric; forming a gate structure in the additional dielectric material; forming a gate dielectric layer on the gate structure and the additional dielectric material; forming a thin channel material on the gate dielectric; forming source and drain regions in electrical contact with the thin channel material to form a transistor; and passivating the transistor and providing electrical access to the source and drain regions. | 06-05-2014 |
20150311457 | FORMING PN JUNCTION CONTACTS BY DIFFERENT DIELECTRICS - A carbon nanotube transistor and method of manufacturing a carbon nanotube transistor is disclosed. The carbon nanotube transistor includes a carbon nanotube on a substrate, a gate electrode deposited on the carbon nanotube, and at least one of a source electrode and a drain electrode deposited on the carbon nanotube and separated from the gate electrode by a space region. The carbon nanotube is doped at the gate electrode an in the space region to form a p-n junction. | 10-29-2015 |
20150325672 | GRAPHENE DEVICES WITH LOCAL DUAL GATES - An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer. | 11-12-2015 |
Shu-Jen Han, Cortlandt, NY US
Patent application number | Description | Published |
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20130175633 | CONTROLLING THRESHOLD VOLTAGE IN CARBON BASED FIELD EFFECT TRANSISTORS - A field effect transistor fabrication method includes defining a gate structure on a substrate, depositing a dielectric layer on the gate structure, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, annealing the first and second metal layers, and defining a carbon based device on the dielectric layer and the gate structure. | 07-11-2013 |
20140091370 | TRANSISTOR FORMATION USING COLD WELDING - A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device. | 04-03-2014 |
20140094006 | TRANSISTOR FORMATION USING COLD WELDING - A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device. | 04-03-2014 |
20150311179 | TRANSISTOR FORMATION USING COLD WELDING - A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device. | 10-29-2015 |
Shu-Jen Han, New York, NY US
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20140147675 | STRUCTURE AND METHOD FOR A GRAPHENE-BASED APPARATUS - An approach is provided for a structure and a method for a graphene-based apparatus. The method comprises acts of forming a graphene layer on a metal layer; forming a protective layer on the graphene layer that makes the graphene layer disposed between the metal layer and the protective layer; transferring the protective layer with the graphene layer and the metal layer onto a substrate; removing the metal layer off from the graphene layer; and forming a conducting layer on the graphene layer. Accordingly, the proposed structure of the graphene-based apparatus is able to prevent graphene damage during the transferring, and because of he use of the protective layer in the structure, the roller can be used to apply the stress which enables roll-to-roll type process and significantly improves the manufacturing throughput. | 05-29-2014 |
Sung Su Han, Niskayuna, NY US
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20100283033 | CARBIDE NANOSTRUCTURES AND METHODS FOR MAKING SAME - A structure includes a substrate and a metallized carbon nano-structure extending from a portion of the substrate. In a method of making a metallized carbon nanostructure, at least one carbon structure formed on a substrate is placed in a furnace. A metallic vapor is applied to the carbon nanostructure at a preselected temperature for a preselected period of time so that a metallized nanostructure | 11-11-2010 |
Taejoon Han, Clifton Park, NY US
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20150021694 | INTEGRATED CIRCUITS HAVING REPLACEMENT METAL GATES WITH IMPROVED THRESHOLD VOLTAGE PERFORMANCE AND METHODS FOR FABRICATING THE SAME - Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a chamfered surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench. | 01-22-2015 |
20150024584 | METHODS FOR FORMING INTEGRATED CIRCUITS WITH REDUCED REPLACEMENT METAL GATE HEIGHT VARIABILITY - Methods for fabricating integrated circuits with reduced replacement metal gate height variability are provided. In an embodiment, a method includes providing a semiconductor substrate with a fin supported thereon and forming a conformal material layer overlying the fin and the semiconductor substrate. A trench is etched within the conformal material layer such that the trench exposes a surface of the fin and the semiconductor substrate. A conductive gate structure is formed within the trench, the conformal material layer is removed, and spacers are formed on the sidewalls of the conductive gate. | 01-22-2015 |
20150069515 | INTEGRATED CIRCUITS HAVING LATERALLY CONFINED EPITAXIAL MATERIAL OVERLYING FIN STRUCTURES AND METHODS FOR FABRICATING SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction. | 03-12-2015 |
20150076111 | FEATURE ETCHING USING VARYING SUPPLY OF POWER PULSES - Etching a feature of a structure by an etch system is facilitated by varying supply of radio frequency (RF) power pulses to the etch system. The varying provides at least one RF power pulse, of the supplied RF power pulses, that deviates from one or more other RF power pulses, of the supplied RF power pulses, by at least one characteristic. | 03-19-2015 |
20150132962 | FACILITATING MASK PATTERN FORMATION - Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern. | 05-14-2015 |
20160049495 | SEMICONDUCTOR STRUCTURES WITH COPLANAR RECESSED GATE LAYERS AND FABRICATION METHODS - Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers. | 02-18-2016 |
Tao Han, Clifton Park, NY US
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20150270159 | FABRICATION OF SEMICONDUCTOR STRUCTURES USING OXIDIZED POLYCRYSTALLINE SILICON AS CONFORMAL STOP LAYERS - Semiconductor structure fabrication methods are provided which include: forming one or more trenches and a plurality of plateaus within a substrate structure; providing a conformal stop layer over the substrate structure, including over the plurality of plateaus, the conformal stop layer being or including oxidized polycrystalline silicon; depositing a material over the substrate structure to fill the one or more trenches and cover the plurality of plateaus thereof; and planarizing the material using a slurry to form coplanar surfaces of the material and the conformal stop layer, wherein the slurry reacts with the oxidized polycrystalline silicon of the conformal stop layer to facilitate providing the coplanar surfaces with minimal dishing of the material. Various embodiments are provided, including different methods of providing the conformal stop layer, such as by oxidizing at least an upper portion of polycrystalline silicon, or by performing an in-situ steam growth process. | 09-24-2015 |
Weiguo Han, Albany, NY US
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20120183961 | METHOD FOR FUNCTIONAL TESTING OF SITE-SPECIFIC DNA METHYLATION - Methods and kits are provided for testing the functional effect of methylating different cytosine residues or testing patterns of DNA methylation on gene expression. Methods are also provided for site-specific methylation, as well as methylated DNA constructs. | 07-19-2012 |
20120264619 | MICRORNA AFFINITY ASSAY AND USES THEREOF - The present invention provides methods and kits for determining which microRNAs bind to a target mRNA where the methods comprise the steps of (a) creating a bait sequence from the target mRNA, where the bait sequence comprises a label that binds to a binding agent; (b) adding a mixture of microRNAs to the bait sequence; (c) separating the microRNAs that bind to the bait sequence from those microRNAs that do not bind; and (d) identifying the microRNAs that bind to the bait sequence, wherein the microRNAs identified are those that bind to the target mRNA. | 10-18-2012 |
Weiqiang Han, Weiqiang, NY US
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20090117384 | Titania Nanocavities and Method of Making - Disclosed herein are compositions of metal oxide nanoparticles having regular polyhedral nanocavities, where the metal oxide can be titania, and where the nanoparticles be nanorods. Also disclosed are titania nanoparticles with nanocavities that are doped with dopants. Methods of making metal oxide nanoparticles with nanocavities are also disclosed. Also disclosed are ultraviolet-blocking compositions including metal oxide nanoparticles with nanocavities, as well as methods of enhancing ultraviolet absorbance efficiency of an ultraviolet blocking composition. Additional uses of metal oxide nanoparticles with nanocavities include solar energy conversion systems and lithium-ion batteries. | 05-07-2009 |
Wei-Qiang Han, East Setauket, NY US
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20120251887 | Carbon-Coated Magneli-Phase TinO2n-1 Nanomaterials and a Method of Synthesis Thereof - A novel Magnéli phase nanomaterial with carbon coating is disclosed. The present Magnéli phase material, which can form a nanowire, a nanobelt, a nanoparticle, a nanocrystal, or a nanosheet, includes at least a Magnéli phase core having a substoichiometric composition of titanium oxide having a formula Ti | 10-04-2012 |
Xiaoxing Han, Rochester, NY US
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20130057873 | SYSTEM AND METHOD FOR MEASURING THE RATIO OF FORWARD-PROPAGATING TO BACK-PROPAGATING SECOND HARMONIC-GENERATION SIGNAL, AND APPLICATIONS THEREOF - A method and system that enable the measurement of a second-harmonic-generation-forward/backward (SHG F/B) ratio from an object by performing only a single image scan using via epi-imaging using an epi-detection technique. Two simultaneous SGH images (a forward propagating SHG “F” image and a back propagating SHG “B” image) are generated during the single image scan. A pinhole mirror can be used to separate the F-SHG and the B-SHG, which are detected by separate detectors. | 03-07-2013 |
Yang Han, New York, NY US
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20110160081 | FUNCTIONAL COMPLEMENTATION ASSAY FOR DEFINED GPCR OLIGOMERS - The present invention is directed to, inter alia, a biological reagent that includes a complex having a first GPCR and a second GPCR linked to a G-protein, the linkage between the second GPCR and the G-protein being of a length, which pre-vents productive interaction between the G-protein and the second GPCR, wherein the first GPCR and the second GPCR linked to the G-protein alone are incapable of producing a signal when presented with a ligand. The invention also provides methods of producing such a biological reagent, as well as methods of determining oligomeric GPCR interactions, methods of identifying compounds that have an effect on GPCR oligomers, methods of identifying a compound capable of interacting with GPCR oligomers, methods of identifying a compound having the ability to modulate binding between a GPCR oligomer and its ligand, and methods for evaluating differential G-protein coupling. | 06-30-2011 |
Yongbin Han, Syracuse, NY US
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20080199950 | Enhanced Bio-Assays By Using Gradient Nanotopgraphy - ABSTRACT A system and method for using gradient nanotopography to increase mammalian cell attachment and cell confinement on surfaces. A surface platform consisting of a thin film of gold possessing a gradient of topography on the surface and self-assembled monolayers of alkanethiols presenting desired functional groups is formed. A gradient in the chemical properties is induced in the terminal groups of the monolayer because of the continuous increase in the surface area and the anisotropy of gold film structure. The gradient nanotopraphy provides simultaneous control of two key properties, the presentation of the terminal functional groups and a continuous increase in the surface density of functional groups on the surface. This control provides for drug screening assays using adherent cell-based experiments. | 08-21-2008 |
Yoon-Chi Han, New York, NY US
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20110178159 | INHIBITORY RNAS THAT REGULATE HEMATOPOIETIC CELLS - Provided are compositions and methods for preventing, treating, ameliorating or diagnosing conditions or diseases involving a myeloid cell proliferation disorder. Such compositions and methods target miRNA function myeloproliferative diseases. More particularly, such compositions and methods target miR-29a function in myeloid cell proliferation disorders. Also provided are methods for diagnosing risk or presence of a myeloid cell proliferation disorder in a subject. | 07-21-2011 |
Yufeng Han, Rochester, NY US
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20080197854 | Harmonic Derived Arc Detector - An arc detection system includes a radio frequency (RF) signal probe that senses a RF signal at an input of a RF plasma chamber and that generates a signal based on at least one of the voltage, current, and power of the RF signal. A signal analyzer receives the signal, monitors the signal for frequency components that have a frequency greater than or equal to a fundamental frequency of the RF signal, and generates an output signal based on the frequency components. The output signal indicates that an arc is occurring in the RF plasma chamber. | 08-21-2008 |
20100201371 | Harmonic Derived Arc Detector - An arc detection system includes a radio frequency (RF) signal probe that senses a RF signal at an input of a RF plasma chamber and that generates a signal based on at least one of the voltage, current, and power of the RF signal. A signal analyzer receives the signal, monitors the signal for frequency components that have a frequency greater than or equal to a fundamental frequency of the RF signal, and generates an output signal based on the frequency components. The output signal indicates that an arc is occurring in the RF plasma chamber. | 08-12-2010 |
Zhiji Han, Rochester, NY US
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20150290615 | METHODS FOR PRODUCING HYDROGEN USING NANOPARTICLE-CATALYST MIXTURES - Provided are compositions for and methods of producing hydrogen. For example, the compositions comprise nanocrystals, a catalyst, a source of electrons, and an aqueous medium. The nanocrystals, catalyst, aqueous medium, and, optionally, the source of electrons are present as a mixture. The methods produce hydrogen by exposing the compositions to electromagnetic radiation (e.g., solar flux). | 10-15-2015 |