Patent application number | Description | Published |
20090219746 | Circuit Arrangement Comprising a Non-Volatile Memory Cell and Method - The circuit arrangement comprises a symmetrically constructed comparator ( | 09-03-2009 |
20090267817 | Adjustable Analogue-Digital Converter Arrangement and Method for Analogue-To-Digital Conversion - An adjustable analog-digital converter arrangement comprising: an input adapted for receiving an input signal; an analog-digital converter operating by successive approximation, having a signal input coupled with the input, wherein said converter is adapted for converting an analog signal at the signal input into a digital value; an attenuator with an output, wherein an input of said attenuator is coupled to the signal input and is adapted for an amplitude change of signals applied to its input, wherein the amplitude change is controllable by means of a control input, and wherein the attenuator comprises switchable capacitors and forms a part of a first stage of said analog-digital converter; a control circuit having an output coupled to the control input of the attenuator and adapted to initialize, as a function of a comparison of a signal output by the analog-digital converter with a threshold, an automatic adjustment of the attenuation by generating a control signal, and having an output for the output of the control signal that is coupled to the attenuator. | 10-29-2009 |
20100060500 | Analog/Digital Converter Assembly and Corresponding Method - An analogue/digital converter arrangement and a method. A differential input voltage is converted by means of a differentially implemented capacitative voltage divider that comprises two programmable capacitor banks ( | 03-11-2010 |
20100220532 | Readout Circuit for Rewritable Memories and Readout Method for Same - In one embodiment, a readout circuit for rewritable memories comprises a control logic unit with an input for supplying a start signal and with several outputs for providing a respective control signal as a function of start signal, a first terminal for switchable connection to a first memory cell by means of a first switch, and a second terminal for switchable connection by means of a second switch to a second memory cell, and a readout unit coupled to the control logic unit, as well as to the first and second terminals, with an output for providing an output signal as a function of a state of the first and/or the second memory cell and as a function of the control signals, wherein the readout circuit is designed for self-terminating operation in a reading mode and in a test mode. A readout method for rewritable memories is additionally provided. | 09-02-2010 |
20100277966 | Memory Array and Storage Method - A memory arrangement comprises a first memory transistor ( | 11-04-2010 |
20100327985 | Oscillator Circuit and Method for Generating a Clock Signal - An oscillator circuit comprises a charging block ( | 12-30-2010 |
20110050325 | Circuit Arrangement for Voltage Supply and Method - The circuit arrangement for the supply of voltage comprises a control arrangement ( | 03-03-2011 |
20110063921 | Circuit Arrangement with a Column Latch and Method for Operating a Column Latch - In one embodiment, a circuit arrangement with a column latch has a first terminal (A | 03-17-2011 |
20130300495 | CHARGE PUMP CIRCUIT AND METHOD FOR GENERATING A SUPPLY VOLTAGE - A charge pump circuit ( | 11-14-2013 |