Patent application number | Description | Published |
20130083902 | Unique Global Identifier Header for Minimizing Prank Emergency 911 Calls - A prank call server that performs 911 prank call filtering over a 911 emergency call system, prior to routing a 911 call to a PSAP. The inventive prank call server identifies prank calling devices, regardless of current service subscription, by retrieving and analyzing emergency call data pertaining to detected prank 911 calls. The prank call server assigns a unique global identifier to each 911 call detected on the 911 emergency call system. Unique global identifiers enable a PSAP to uniquely identify prank 911 calls that are identified thereon. A PSAP transmits a prank call signal and a relevant unique global identifier to the prank call server, for each prank 911 call that is detected. A prank call signal/unique global identifier combination triggers the prank call server to store all available call data for a referenced prank 911 call in to a prank call database, for subsequent prank call filtering analysis. | 04-04-2013 |
20130086274 | Timing Management for Implementing Smarter Decisions in Time-Constrained Complex Distribution Systems - A timing management node that assigns and adjusts timeout values for a time-constrained complex distributed system based on the nature of a system request, preferences of a customer furnishing a system request, and/or a current state of a complex distributed system. A timing management node evaluates information regarding a system request and information regarding a current state of a complex distributed system to generate timing requirements for the system request. Timing requirements are compiled in a timing policy messager and passed amongst nodes of a complex distributed system with process flow. Timing requirements may be revised during request processing to reflect events that have occurred within the distributed system. A timing policy message contains a timeout value and a total time elapsed parameter for a system request, to permit a complex distributed system to make smarter processing decisions based on a known time remaining to process the given system request. | 04-04-2013 |
20140341358 | Unique Global Identifier Header for Minimizing Prank 911 Calls - A prank call server that performs 911 prank call filtering over a 911 emergency call system, prior to routing a 911 call to a PSAP. The inventive prank call server identifies prank calling devices, regardless of current service subscription, by retrieving and analyzing emergency call data pertaining to detected prank 911 calls. The prank call server assigns a unique global identifier to each 911 call detected on the 911 emergency call system. Unique global identifiers enable a PSAP to uniquely identify prank 911 calls that are identified thereon. A PSAP transmits a prank call signal and a relevant unique global identifier to the prank call server, for each prank 911 call that is detected. A prank call signal/unique global identifier combination triggers the prank call server to store all available call data for a referenced prank 911 call in to a prank call database, for subsequent prank call filtering analysis. | 11-20-2014 |
20160006869 | Unique Global Identifier Header for Minimizing Prank Emergency 911 Calls - A prank call server that performs 911 prank call filtering over a 911 emergency call system, prior to routing a 911 call to a PSAP. The inventive prank call server identifies prank calling devices, regardless of current service subscription, by retrieving and analyzing emergency call data pertaining to detected prank 911 calls. The prank call server assigns a unique global identifier to each 911 call detected on the 911 emergency call system. Unique global identifiers enable a PSAP to uniquely identify prank 911 calls that are identified thereon. A PSAP transmits a prank call signal and a relevant unique global identifier to the prank call server, for each prank 911 call that is detected. A prank call signal/unique global identifier combination triggers the prank call server to store all available call data for a referenced prank 911 call in to a prank call database, for subsequent prank call filtering analysis. | 01-07-2016 |
Patent application number | Description | Published |
20090327986 | GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT WITH TIMING EXCEPTION PATHS - Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression. | 12-31-2009 |
20100191679 | METHOD AND APPARATUS FOR CONSTRUCTING A CANONICAL REPRESENTATION - Some embodiments provide systems and techniques to facilitate construction of a canonical representation (CR) which represents a logical combination of a set of logical functions. During operation, the system can receive a CR-size limit. Next, the system can construct a set of CRs based on the set of logical functions, wherein each CR in the set of CRs represents a logical function in the set of logical functions. The system can then combine a subset of the set of CRs to obtain a combined CR. Next, the system can identify a problematic CR which when combined with the combined CR causes the CR-size limit to be exceeded. The system can then report the problematic CR and/or a logical function associated with the problematic CR to a user, thereby helping the user to identify an error in the set of logical functions. | 07-29-2010 |
20100275169 | ADAPTIVE STATE-TO-SYMBOLIC TRANSFORMATION IN A CANONICAL REPRESENTATION - Some embodiments provide a system for adaptively performing state-to-symbolic transformation in a canonical representation which is used for generating random stimulus for a constrained-random simulation. The system can construct a canonical representation for a set of constraints using the set of random variables and the subset of the state variables in the constraints. Next, the system can use the canonical representation to generate random stimulus for the constrained-random simulation, and monitor parameters associated with the constrained-random simulation. Next, the system can add state variables to or remove state variables from the canonical representation based at least on the monitored parameters. The system can then use the modified canonical representation which has a different set of state variables to generate random stimulus for the constrained-random simulation. | 10-28-2010 |
20120136635 | METHOD AND APPARATUS FOR OPTIMIZING CONSTRAINT SOLVING THROUGH CONSTRAINT REWRITING AND DECISION REORDERING - Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints. | 05-31-2012 |
20120227022 | Technique For Honoring Multi-Cycle Path Semantics In RTL Simulation - An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of magnitude faster than gate level simulation. Moreover, design bugs associated with multi-cycle paths are more easily corrected during RTL simulation compared to waiting until the gate level simulation. | 09-06-2012 |
20120253754 | METHOD AND APPARATUS FOR IDENTIFYING INCONSISTENT CONSTRAINTS - Methods and apparatuses are described for identifying inconsistent constraints. During operation, a system can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. If an inconsistency or conflict is detected while solving the set of constraints, the system can identify a phase in a series of phases of the constraint solver where the inconsistency was detected. The system can then try to solve different subsets of the set of constraints to identify smaller subsets of the set of constraints that contain the inconsistency. When the system tries to solve a subset of the set of constraints, the system can determine whether or not an inconsistency is detected in the identified phase while solving the subset of the set of constraints. Next, the system can report the smallest subset of inconsistent constraints that was found to a user. | 10-04-2012 |
20120278675 | METHOD AND APPARATUS FOR PERFORMING IMPLICATION AND DECISION MAKING USING MULTIPLE VALUE SYSTEMS DURING CONSTRAINT SOLVING - Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. An embodiment can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. Next, the embodiment can generate a circuit model based on the set of constraints, wherein assignable values for at least one node in the circuit model are represented in multiple value systems. The embodiment can then assign random values to the set of random variables based on the circuit model. | 11-01-2012 |
20140067356 | INFORMATION THEORETIC CACHING FOR DYNAMIC PROBLEM GENERATION IN CONSTRAINT SOLVING - Computer-implemented techniques are disclosed for verifying circuit designs using dynamic problem generation. A device under test (DUT) is modeled as part of a test bench where the test bench is a random process. A set of constraints is solved to generate stimuli for the DUT. Problem generation is repeated numerous times throughout a verification process with problems and sub-problems being generated and solved. When a problem is solved, the problem structure can be stored in a cache. The storage can be based on entropy of variables used in the problem. The problem storage cache can be searched for previously stored problems which match a current problem. By retrieving a problem structure from cache, the computational burden is reduced during verification. Problems can be multi-phase problems with storage and retrieval of problem structures based on the phase level. Caching can be accomplished using an information theoretic approach. | 03-06-2014 |
20140068533 | INFORMATION THEORETIC SUBGRAPH CACHING - Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be stored in a cache. The storage can be based on entropy of variables used in the graph and subgraph problems. The subgraph problem storage cache can be searched for previously stored problems which match another problem in need of a solution. By retrieving subproblem variables, values, and information from the cache, the computational overhead of circuit design verification is reduced as problems are reused. Caching can be accomplished using an information theoretic approach. | 03-06-2014 |
20140282316 | SOLVING MULTIPLICATION CONSTRAINTS BY FACTORIZATION - A design description for verification includes a set of constraints on random variables within the design description. The set of constraints includes at least one multiplication constraint involving at least two random variables. A computer-based tool obtains designs and analyzes the design description to find the set of constraints and identify the multiplication constraint. The computer-based tool then performs factorization to solve for the multiplication constraint and to determine a set of potentially valid factoring values for the random variables used in the multiplication constraint. The design problem is then solved by the computer-based tool using the factoring values. If two multiplication constraints involve a common variable, the factorization finds a set of common factoring values between the two multiplication constraints to use for the common variable. | 09-18-2014 |
20140282343 | PRIORITIZED SOFT CONSTRAINT SOLVING - A design problem can include a mixture of hard constraints and soft constraints. The soft constraints can be prioritized and the design problem solved. One or more soft constraints may not be honored in the midst of the solving of the design problem. Debugging can be performed and the unsatisfied soft constraints identified. Root-cause analysis can evaluate the challenges within the design problem which caused soft constraints not to be honored. | 09-18-2014 |
20150067622 | DEVELOPMENT AND DEBUG ENVIRONMENT IN A CONSTRAINED RANDOM VERIFICATION - A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage. | 03-05-2015 |
20160034624 | OPTIMIZING CONSTRAINT SOLVING BY REWRITING AT LEAST ONE BIT-SLICE CONSTRAINT - Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints. | 02-04-2016 |
Patent application number | Description | Published |
20090105956 | Methodology and Application of Multimodal Decomposition of a Composite Distribution - A method for analyzing formation data includes decomposing the formation data into simple components that can be used to reconstruct the formation data, wherein the decomposing is performed at a first location and includes a process to minimize an overlap between the simple components; and transmitting parameters representing the simple components to a second location for reconstructing the formation data. A system for analyzing formation data that includes a processor and a memory that stores a program having instructions for decomposing the formation data into simple components that can be used to reconstruct the formation data, wherein the decomposing is performed at a first location and includes a process to minimize an overlap between the simple components; and transmitting parameters representing the simple components to a second location for reconstructing the formation data. | 04-23-2009 |
20090260879 | MAGNETIC RANGING WHILE DRILLING USING AN ELECTRIC DIPOLE SOURCE AND A MAGNETIC FIELD SENSOR - A system and methods for drilling a well in a field having an existing well are provided. In accordance with one embodiment, a method of drilling a new well in a field having an existing well includes drilling the new well using a bottom hole assembly (BHA) having a drill collar divided by an insulated gap, generating a current on the drill collar of the BHA while drilling the new well, and measuring from the existing well a magnetic field caused by the current on the drill collar of the BHA. Using measurements of the magnetic field, the relative position of the new well to the existing well may be determined. | 10-22-2009 |
20110087459 | CLEANUP PREDICTION AND MONITORING - The examples described herein relate to methods and apparatus for cleanup prediction and monitoring. A disclosed method of predicting cleanup of a sample fluid obtained by a downhole tool includes drawing the sample fluid into the downhole tool via a probe assembly; measuring optical densities of the sample fluid at a plurality of different respective times; selecting at least some of the measured optical densities as fitting points; identifying one or more inversion parameters; and performing, via a processor, an inversion using the fitting points, the inversion parameters and simulation data to generate data associated with a predicted cleanup of the sample fluid. | 04-14-2011 |
20140069721 | MAGNETIC RANGING WHILE DRILLING USING AN ELECTRIC DIPOLE SOURCE AND A MAGNETIC FIELD SENSOR - A system and methods for drilling a well in a field having an existing well are provided. Specifically a method of drilling a new well in a field having an existing well includes drilling the new well using a bottom hole assembly (BHA) having a drill collar divided by an insulated gap, generating a current on the drill collar of the BHA while drilling the new well, and measuring from the existing well a magnetic field caused by the current on the drill collar of the BHA. Using measurements of the magnetic field, a relative position of the new well to the existing well may be determined. | 03-13-2014 |
20150192694 | Robust Well Log Sharpening With Unknown Tool Response Function - A method for enhancing axial resolution of a well logging instrument includes classifying a formation into a plurality of single well log measurement value zones to generate a squared well log. A response function of a well logging instrument is decomposed into a plurality of wavelets. The wavelets are convolved with the squared well log to generate a simulated tool response. The simulated tool response is compared to a measured tool response in the formation. The decomposing is repeated with different coefficients for each wavelet and the convolving is repeated until a mismatch between the simulated tool response and the measured tool response falls below a measurement uncertainty of the well logging instrument. | 07-09-2015 |
Patent application number | Description | Published |
20080246124 | PLASMA TREATMENT OF INSULATING MATERIAL - A method is disclosed which includes forming an opening in an insulating material, performing a plasma process to introduce nitrogen into a portion of the insulating material to thereby form a nitrogen-containing region at least on an inner surface of the opening, and, after forming the nitrogen-containing region, performing an etching process through the opening. A device is disclosed which includes an insulating material comprising a nitrogen-enhanced region that is proximate an opening that extends through the insulating material and a conductive structure positioned within the opening. | 10-09-2008 |
20080273410 | Tungsten digitlines - Methods, devices, and systems for using and forming tungsten digitlines have been described. The tungsten digitlines formed according to embodiments of the present disclosure can be formed with a tungsten (W) monolayer on a tungsten nitride (WN | 11-06-2008 |
20090032949 | Method of depositing Tungsten using plasma-treated tungsten nitride - Devices structures utilizing, and methods of forming, tungsten interconnects in semiconductor fabrication are disclosed. Tungsten deposition is accomplished by a three-step process that does not require a resistive nucleation material to be deposited prior to bulk tungsten deposition. By treating a tungsten nitride material with a hydrogen plasma, thereby reducing the tungsten nitride to tungsten, the necessity of a resistive nucleation layer is eliminated. Other embodiments describe methods of tungsten deposition requiring a thinner resistive nucleation material (<10 angstroms) than currently known. | 02-05-2009 |
20090283907 | LOW-RESISTANCE INTERCONNECTS AND METHODS OF MAKING SAME - Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench. | 11-19-2009 |
20100171178 | SEMICONDUCTOR DEVICES INCLUDING DUAL GATE STRUCTURES AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES - Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed. | 07-08-2010 |
20110095427 | LOW-RESISTANCE INTERCONNECTS AND METHODS OF MAKING SAME - Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench. | 04-28-2011 |
20110216585 | METAL CONTAINING MATERIALS - Metal containing materials and methods of forming the same are disclosed. One such method includes substantially concurrently feeding a flow of precursor gas containing a metal of a metal containing material and a flow of source gas containing a reducing agent so that the precursor gas and the source gas react to form a thickness of the metal containing material. The flow of precursor gas is discontinued, and while the flow of precursor gas is discontinued, the flow of source gas continues to be fed to contact the thickness of the metal containing material. | 09-08-2011 |
20110254072 | CHARGE STORAGE STRUCTURES AND METHODS - Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor. | 10-20-2011 |
20110309324 | SOLID STATE DEVICES WITH SEMI-POLAR FACETS AND ASSOCIATED METHODS OF MANUFACTURING - Solid state lighting devices with semi-polar or non-polar surfaces and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and an epitaxial silicon structure in direct contact with the substrate surface. The epitaxial silicon structure has a sidewall extending away from the substrate surface. The solid state lighting device also includes a semiconductor material on at least a portion of the sidewall of the epitaxial silicon structure. The semiconductor material has a semiconductor surface that is spaced apart from the substrate surface and is located on a semi-polar or non-polar crystal plane of the semiconductor material. | 12-22-2011 |
20120199807 | SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING A DIODE STRUCTURE AND METHODS OF FORMING SAME - Methods of forming diode structures for use in memory cells and memory arrays, such as resistive random access memory (RRAM). The methods include forming a first electrode by chemisorbing a graphite material (e.g., graphene) on a conductive material. A low-k dielectric material may be formed over surfaces of the first electrode exposed through an opening in a dielectric material overlying the first electrode, followed by formation of a high-k dielectric material over the low-k dielectric material. A remaining portion of the opening may be filled with another conductive material to form a second electrode. The first and second electrodes of the resulting diode structure have different work functions and, thus, provide a low thermal budget, a low contact resistance, a high forward-bias current and a low reverse-bias current. A memory cell and a memory array including such a diode structure are also disclosed. | 08-09-2012 |
20120256269 | SEMICONDUCTOR DEVICES INCLUDING DUAL GATE STRUCTURES AND METHODS OF FABRICATION - Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed. | 10-11-2012 |
20120258585 | INCORPORATING IMPURITIES USING A DISCONTINUOUS MASK - Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a discontinuous mask. | 10-11-2012 |
20130214248 | SOLID STATE LIGHTING DEVICES WITH SEMI-POLAR FACETS AND ASSOCIATED METHODS OF MANUFACTURING - Solid state lighting devices with semi-polar or non-polar surfaces and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and an epitaxial silicon structure in direct contact with the substrate surface. The epitaxial silicon structure has a sidewall extending away from the substrate surface. The solid state lighting device also includes a semiconductor material on at least a portion of the sidewall of the epitaxial silicon structure. The semiconductor material has a semiconductor surface that is spaced apart from the substrate surface and is located on a semi-polar or non-polar crystal plane of the semiconductor material. | 08-22-2013 |
20130264713 | METHODS OF FORMING CONDUCTIVE STRUCTURES AND METHODS OF FORMING DRAM CELLS - Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions. | 10-10-2013 |
20130295760 | INCORPORATING IMPURITIES USING A MASK - Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a mask. | 11-07-2013 |
20140010018 | NANODOT CHARGE STORAGE STRUCTURES AND METHODS - Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor. | 01-09-2014 |
20140048943 | Semiconductor Constructions, Methods of Forming Conductive Structures and Methods of Forming DRAM Cells - Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions. | 02-20-2014 |
20140117302 | Phase Change Memory Cells, Methods Of Forming Phase Change Memory Cells, And Methods Of Forming Heater Material For Phase Change Memory Cells - A phase change memory cell includes a pair of electrodes having phase change material and heater material there-between. An electrically conductive thermal barrier material is between one of the electrodes and the heater material. Methods are disclosed. | 05-01-2014 |
20140248760 | METHODS OF FORMING DUAL GATE STRUCTURES - Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed. | 09-04-2014 |
20150303147 | Semiconductor Constructions, Methods of Forming Conductive Structures and Methods of Forming DRAM Cells - Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions. | 10-22-2015 |
20160118340 | Low-Resistance Interconnects and Methods of Making Same - Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench. | 04-28-2016 |
Patent application number | Description | Published |
20100249687 | TOE BRACE DESIGNS - In various embodiments, provided are braces for use in supporting the metatarsophalangeal joint, reducing or maintaining the intermetatarsal angle, enhancing or maintaining alignment of the hallux, or combinations thereof in a subject having hallux valgus. | 09-30-2010 |
20100249942 | TOE JOINT REPLACEMENT MODELS - In various embodiments, provided are implantable devices for replacing all or a portion of a metatarsophalangeal joint, comprising (i) a metatarsal component comprising a substantially convex bearing surface; or (ii) a phalanx component comprising a substantially concave bearing surface; or (iii) both. In various embodiments, also provided are methods of treating hallux valgus by replacing all or a portion of a metatarsophalangeal joint with one or more of the provided implantable devices. | 09-30-2010 |
20120330207 | TOE BRACE DESIGNS - In various embodiments, provided are braces for use in supporting the metatarsophalangeal joint, reducing or maintaining the intermetatarsal angle, enhancing or maintaining alignment of the hallux, or combinations thereof in a subject having hallux valgus. | 12-27-2012 |
20130046387 | TOE JOINT REPLACEMENT MODELS - In various embodiments, provided are implantable devices for replacing all or a portion of a metatarsophalangeal joint, comprising (i) a metatarsal component comprising a substantially convex bearing surface; or (ii) a phalanx component comprising a substantially concave bearing surface; or (iii) both. In various embodiments, also provided are methods of treating hallux valgus by replacing all or a portion of a metatarsophalangeal joint with one or more of the provided implantable devices. | 02-21-2013 |