Patent application number | Description | Published |
20090100320 | END-TO-END CYCLIC REDUNDANCY CHECK PROTECTION FOR HIGH INTEGRITY FIBER TRANSFERS - A method, transceiver, and computer program storage product transfer data over fiber between a first transceiver and a second transceiver. The second transceiver is determined to support a high integrity cyclic redundancy check associated with substantially an entire data set in a Fibre Channel Protocol exchange between the first transceiver and the second transceiver. A last data frame in a plurality of data frames is formatted for communication to the second transceiver during the Fibre Channel Protocol exchange. The last data frame includes a plurality of data and at least one cyclic redundancy check field associated with the plurality data and at least one additional cyclic redundancy check field associated with the plurality of data frames. | 04-16-2009 |
20110106990 | EFFICIENT HANDLING OF QUEUED-DIRECT I/O REQUESTS AND COMPLETIONS - Computer program products and methods for efficient handling of queued-direct input/output (QDIO) requests and completions at an adapter in communication with an I/O device are provided. A method includes accessing a queue with one or more storage block address lists (SBALs), where each SBAL includes a plurality of storage block address list entries (SBALEs) and is associated with an SLSB. The method further includes reading an SBAL count in one of the SBALEs, where the SBAL count indicates a number of the SBALs forming an I/O request to the I/O device. In response to determining that the SBAL count is greater than one, a number of the SBALs from the queue and associated SLSBs equivalent to the SBAL count are prefetched without waiting for a notification of completion of each of the SBALs forming the I/O request, and states of the associated SLSBs transition from adapter-owned to program-owned. | 05-05-2011 |
20120311201 | PARTITIONING OF A VARIABLE LENGTH SCATTER GATHER LIST - Partitioning of a variable length scatter gather list including a processor for performing a method that includes requesting data from an I/O device comprising an I/O buffer. The requesting includes initiating a subchannel. The method further includes determining whether the subchannel supports data divisions by requesting SSQD data from the I/O device and inspecting at least one bit in the SSQD data. A determination is made whether the requested data includes a metadata block in response to determining that the subchannel support data divisions. Also, the subchannel is notified that the requested data includes the metadata block in response to determining that the requested data includes the metadata block. A location of storage is identified in an SBAL in response to notifying the subchannel. | 12-06-2012 |
20120311217 | FACILITATING PROCESSING OF OUT-OF-ORDER DATA TRANSFERS - Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer. | 12-06-2012 |
20120311218 | FACILITATING PROCESSING OF OUT-OF-ORDER DATA TRANSFERS - Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer. | 12-06-2012 |
20120311544 | SYSTEM AWARE PERFORMANCE COUNTERS - System aware performance counters including a processor for performing a method that includes executing a predefined code segment of an application, the executing on a processor. The executing includes executing an instrumented thread included in the predefined code segment. The method includes performing a first action associated with executing the instrumented thread in the predefined code segment, and registering the instrumented thread. A performance counter associated with the predefined code segment is started. Also, the execution of the predefined code segment is paused and the performance counter is paused. The method further includes performing a second action associated with pausing the executing of the predefined code segment. The executing of the predefined code segment is resumed and the performance counter is resumed responsive to resuming the executing of the predefined code segment. Also, a third action associated with resuming executing the predefined code segment is performed. | 12-06-2012 |
20120311716 | SIMULTANEOUS MIXED PROTECTION MODES OVER A VIRTUALIZED HOST ADAPTER - A method for supporting simultaneous mixed protection modes for a write operation. The method includes receiving a write request that includes write data, and is received from one of a plurality of requestors. At least one of the requestors does not support data integrity protection. It is determined if data integrity protection is required for the write operation. It is additionally determined if the data integrity protection is supported by the requestor. Once the determination is made, the data integrity protection value is calculated if data integrity protection is required and is not supported by the requestor. The write data is encoded with the data integrity protection value prior to being written. If the requestor supports data integrity protection, then data integrity protection values are applied to the write data prior to writing the data to the external storage. | 12-06-2012 |
20140258561 | FACILITATING PROCESSING OF OUT-OF-ORDER DATA TRANSFERS - Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer. | 09-11-2014 |