Ganfield
Dan Ganfield, Ramsey, MN US
Patent application number | Description | Published |
---|---|---|
20110290743 | HELICAL SUPPORT STRUCTURE FOR INTAKE SCREENS - A method and apparatus for supporting a screen. The apparatus comprising a cylindrical screen for submerging in a fluid, the screen having an inlet pipe for connecting to a piping system, filter members, a first end, a second and a support structure. The support structure is one or more helical members which traverse the screen. | 12-01-2011 |
20130001148 | FILTER ASSEMBLY - A method and apparatus for supporting a screen. The apparatus may comprise a cylindrical screen for submerging in a fluid. The screen may have an inlet pipe for connecting to a piping system, filter members, a first end, a second end, and a support structure. The support structure may include one or more helical and/or straight bar members which traverse the screen. | 01-03-2013 |
Paul A. Ganfield, Rochester, MN US
Patent application number | Description | Published |
---|---|---|
20080229007 | Enhancements to an XDR Memory Controller to Allow for Conversion to DDR2 - A memory control apparatus includes a data stream format converter and a physical layer converter. The data stream format converter is configured to convert an incoming data stream that has a data stream format corresponding to a first memory type into a format-converted data stream that has a data stream format corresponding to a second memory type. The second memory type is different from the first memory type. The physical layer converter is configured to convert the format-converted data stream into a physical-layer-converted data stream that has at least one physical parameter corresponding to the second memory type. The format-converted data stream has at least one physical parameter corresponding to the first memory type. | 09-18-2008 |
20110047352 | MEMORY COHERENCE DIRECTORY SUPPORTING REMOTELY SOURCED REQUESTS OF NODAL SCOPE - A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node. | 02-24-2011 |
20120203976 | MEMORY COHERENCE DIRECTORY SUPPORTING REMOTELY SOURCED REQUESTS OF NODAL SCOPE - A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node. | 08-09-2012 |
Paul Allen Ganfield, Rochester, MN US
Patent application number | Description | Published |
---|---|---|
20080307184 | MEMORY CONTROLLER OPERATING IN A SYSTEM WITH A VARIABLE SYSTEM CLOCK - The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access. | 12-11-2008 |
20090119442 | Managing Write-to-Read Turnarounds in an Early Read After Write Memory System - Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank. | 05-07-2009 |