Patent application number | Description | Published |
20080307240 | POWER MANAGEMENT ELECTRONIC CIRCUITS, SYSTEMS, AND METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit including a power managed circuit ( | 12-11-2008 |
20090039952 | System and Method for Auto-Power Gating Synthesis for Active Leakage Reduction - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 02-12-2009 |
20090046519 | METHOD, DEVICE AND SYSTEM FOR CONFIGURING A STATIC RANDOM ACCESS MEMORY CELL FOR IMPROVED PERFORMANCE - A computer-implemented method of configuring a static random access memory (SRAM) bit cell for operation, an adaptive biasing device and semiconductor wafer testing system. In one embodiment, the method includes: (1) determining a performance characteristic of the SRAM bit cell on a wafer, (2) comparing the performance characteristic to a target and (3) configuring biasing circuitry associated with the SRAM bit cell based on the comparing. | 02-19-2009 |
20100103760 | Memory Power Management Systems and Methods - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 04-29-2010 |
20100253387 | SYSTEM AND METHOD FOR AUTO-POWER GATING SYNTHESIS FOR ACTIVE LEAKAGE REDUCTION - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 10-07-2010 |
20100287517 | Statistical Static Timing Analysis in Non-Linear Regions - A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths. | 11-11-2010 |
20110216619 | MEMORY POWER MANAGEMENT SYSTEMS AND METHODS - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 09-08-2011 |
20130033295 | CLOCK PHASE COMPENSATION FOR ADJUSTED VOLTAGE CIRCUITS - Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are generated with the second input clock having a phase that is programmably shifted relative to the first input clock when the system is operating at a lowered operating voltage or different temperature, for example. The first and second input clocks are coupled to a dually clocked flip flop, each having a primary latch and a secondary latch. A composite clock signal is generated in response to the first input clock and the second input clock. For example, a first signal is latched in the primary latch in response to the composite clock signal and a second signal is latched in the secondary latch in response to the first input clock signal. | 02-07-2013 |
20130154723 | PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD - The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. | 06-20-2013 |
20140095919 | CLOCK CONTROL METHOD FOR PERFORMANCE THERMAL AND POWER MANAGEMENT SYSTEM - A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period. | 04-03-2014 |
20150022254 | PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD - The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. | 01-22-2015 |
20150022260 | PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD - The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. | 01-22-2015 |
20150025829 | PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD - The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC maybe set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. | 01-22-2015 |
Patent application number | Description | Published |
20090082778 | APPLICATOR, ASSEMBLY, AND METHOD FOR CONNECTING AN INLET CONDUIT TO A HOLLOW ORGAN - The invention provides an applicator for forming a hole in a wall of a hollow organ and for connecting a hemostatic connection assembly to the hollow organ, wherein, when the hole is formed in the wall of the hollow organ, a first fluid seal exists between the hemostatic connection assembly and the wall of the hollow organ and a second fluid seal exists between the hemostatic connection assembly and the applicator, thereby minimizing fluid loss from the hollow organ. The invention further provides a hemostatic connection assembly for connecting an inlet conduit to a hollow organ, the hemostatic connection assembly comprising a organ wall connection portion, a cuff portion, an extension portion, and a seal ring portion, wherein, during the process of connecting the inlet conduit to the hollow organ, a first fluid seal exists between the organ wall connection portion and the wall of the hollow organ, and a second fluid seal exists between the hemostatic connection assembly and the inlet conduit, thereby minimizing fluid loss from the hollow organ. A method is also disclosed in which the applicator and hemostatic connection assemblies of the invention are used to connect an inlet conduit to a hollow organ. | 03-26-2009 |
20100010500 | Apparatus and method for connecting a conduit to a hollow organ - An apparatus and method for connecting a first conduit to the heart without the need for cardiopulmonary bypass. The first conduit may then be attached to a second conduit that has a prosthetic device interposed. The second conduit may then be connected to the aorta. The prosthetic device may be a prosthetic valve or a pump, for example. The apparatus of the present invention includes an implantable connector with first conduit component, a retractor expansion component, a coring component, and a pushing component. The retractor expansion component is slide-ably coupled to the coring component. The retractor expansion component serves to seat against and separate the inside apical wall of the left ventricle so that the coring component may cut cleanly through the myocardium to form a tissue plug without leaving any hanging attachments to the inside walls. By remaining seated against the inside wall, the retractor expansion component follows the tissue plug into the coring component. The surgeon applies force and rotary motion to the pushing component sufficient to cut the tissue plug and implant the prosthetic component. | 01-14-2010 |
20110118763 | METHOD AND APPARATUS FOR EFFECTING AN AORTIC VALVE BYPASS, INCLUDING THE PROVISION AND USE OF A T-STENT FOR EFFECTING A DISTAL ANASTOMOSIS FOR THE SAME - A connector for joining a first hollow structure to the side wall of a second hollow structure, the connector comprising:
| 05-19-2011 |
20110196408 | Apparatus and method for forming a hole in a hollow organ - The invention relates to an apparatus and method for forming a hole in a wall of a hollow organ. The applicator includes a hole forming element for forming a hole in the wall of the organ, a positioning means for positioning the hole forming element, and a retractor element. In addition, the applicator includes a sequencing means for coordinating the relative movement of the retractor element and the hole forming element in a sequential manner to thereby carry out a procedure for forming a hole in the wall of the hollow organ. The sequencing means may further include a safety latch element operatively coupled to the retracting means and the hole forming element. The safety latch of the invention keeps prevents damage to the internal surface of the organ during the formation of the hole. | 08-11-2011 |
20130218261 | APPARATUS AND METHOD FOR CONNECTING A CONDUIT TO A HOLLOW VESSEL - An applicator for forming a hole in a wall of a hollow vessel and engaging a graft, the applicator comprising: a hole forming element adapted to form a hole in the wall of the vessel, the hole forming element comprising a cutting element adapted to cut a hole in the wall of the vessel and a positioning element adapted to hold the position of the applicator relative to the vessel; and an insertion element adapted to be inserted through the wall of the vessel, the insertion element comprising a retraction element adapted to enter into engagement with a graft. | 08-22-2013 |
20140100430 | APPLICATOR, ASSEMBLY, AND METHOD FOR CONNECTING AN INLET CONDUIT TO A HOLLOW ORGAN - The invention provides an applicator for forming a hole in a wall of a hollow organ and for connecting a hemostatic connection assembly to the hollow organ, wherein, when the hole is formed in the wall of the hollow organ, a first fluid seal exists between the hemostatic connection assembly and the wall of the hollow organ and a second fluid seal exists between the hemostatic connection assembly and the applicator, thereby minimizing fluid loss from the hollow organ. The invention further provides a hemostatic connection assembly for connecting an inlet conduit to a hollow organ, the hemostatic connection assembly comprising a organ wall connection portion, a cuff portion, an extension portion, and a seal ring portion, wherein, during the process of connecting the inlet conduit to the hollow organ, a first fluid seal exists between the organ wall connection portion and the wall of the hollow organ, and a second fluid seal exists between the hemostatic connection assembly and the inlet conduit, thereby minimizing fluid loss from the hollow organ. A method is also disclosed in which the applicator and hemostatic connection assemblies of the invention are used to connect an inlet conduit to a hollow organ. | 04-10-2014 |
20140155983 | METHOD AND APPARATUS FOR EFFECTING AN AORTIC VALVE BYPASS, INCLUDING THE PROVISION AND USE OF A T-STENT FOR EFFECTING A DISTAL ANASTOMOSIS FOR THE SAME - A connector for joining first and second hollow structures, comprising a fluid-constraining tube having a fluid-constraining neck extending therefrom, wherein the tube and the neck each comprise a lumen having first and second openings, the neck being joined to the tube such that fluid entering the first opening of the tube can exit the second opening of the tube, and fluid entering the first opening of the neck can exit the second opening of the tube; at least the portions of the tube adjacent to the first and second openings of the tube being biased radially outwardly so that they normally assume a radially-expanded configuration, but being capable of being restrained in a radially-contracted configuration, wherein the tube is sized so that, when it is in its radially-expanded configuration, it has an outer diameter which is larger than the inner diameter of the second hollow structure. | 06-05-2014 |
20150031959 | APPARATUS AND METHOD FOR FORMING A HOLE IN A HOLLOW ORGAN - The invention relates to an apparatus and method for forming a hole in a wall of a hollow organ. The applicator includes a hole forming element for forming a hole in the wall of the organ, a positioning means for positioning the hole forming element, and a retractor element. In addition, the applicator includes a sequencing means for coordinating the relative movement of the retractor element and the hole forming element in a sequential manner to thereby carry out a procedure for forming a hole in the wall of the hollow organ. The sequencing means may further include a safety latch element operatively coupled to the retracting means and the hole forming element. The safety latch of the invention keeps prevents damage to the internal surface of the organ during the formation of the hole. | 01-29-2015 |