Patent application number | Description | Published |
20110084860 | APPARATUS AND METHOD FOR PIPELINED ANALOG TO DIGITAL CONVERSION - Apparatus and methods for pipelined analog-to-digital conversion are disclosed. In some embodiments, a pipelined analog-to-digital converter includes a control and correction circuit; and a plurality of MDAC stages. At least one of the MDAC stages includes: an MDAC input to receive an analog input voltage; and a dual latch flash ADC comprising one or more dual latch comparators. At least one of the dual latch comparators includes: a pre-amplifier having an input coupled to the MDAC input, and an output; a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output; a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch may generate a first digital signal; and a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch may generate a second digital signal. | 04-14-2011 |
20110084861 | APPARATUS AND METHOD FOR PIPELINED ANALOG TO DIGITAL CONVERSION - Apparatus and methods for pipelined analog-to-digital conversion are disclosed. In some embodiments, a pipeline analog-to-digital converter includes a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade. At least one of the MDAC stages includes two or more flash ADCs connected in parallel, operating alternately to generate digital signals from an analog input voltage. In one embodiment, the flash ADCs provide the digital signals in an alternating manner to a capacitor block that receives a delayed analog input voltage. In another embodiment, the at least one MDAC may include two or more capacitor blocks, each of which is associated with a respective one of the flash ADCs, forming two or more sets of a flash ADC and a capacitor block. In yet another embodiment, the at least one MDAC also include three or more capacitor blocks, each of which can be randomly selected for one of the flash ADCs. | 04-14-2011 |
20120242401 | PHASED-ARRAY CHARGE PUMP SUPPLY - A charge pump system and method that may provide large supply voltages and currents with reduced ripple voltage at reduced ripple frequency. The charge pump system may include an array of charge pumps and a delay pipeline. The array of charge pumps may include a plurality of charge pumps. The delay pipeline may include a plurality of delay elements. The delay elements may respond to a global trigger signal to output a trigger signal to the array of charge pumps. Respective charge pumps may fire in response to the trigger signal. | 09-27-2012 |
20120274497 | PIPELINED ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage. | 11-01-2012 |
20130113563 | GAIN ENHANCEMENT FOR CASCODE STRUCTURE - Aspects of the present invention provide apparatuses and methods to provide significant gain enhancement for a cascode structure for a differential amplifier. The cascode structure of the differential amplifier can include first and second pairs of output transistors. The second pair of output transistors can be configured to approximately cancel modulation effects of the first pair of output transistors induced by changes in a differential output of differential amplifier, thereby resulting in conditions for providing enhanced gain. | 05-09-2013 |
20130120173 | PIPELINED ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage. | 05-16-2013 |
20130278336 | GAIN ENHANCEMENT FOR CASCODE STRUCTURE - Aspects of the present invention provide apparatuses and methods to provide significant gain enhancement for a cascode structure for a differential amplifier. The cascode structure of the differential amplifier can include first and second pairs of output transistors. The second pair of output transistors can be configured to approximately cancel modulation effects of the first pair of output transistors induced by changes in a differential output of differential amplifier, thereby resulting in conditions for providing enhanced gain. | 10-24-2013 |
20140340140 | PHASED-ARRAY CHARGE PUMP SUPPLY - A charge pump system and method that may provide large supply voltages and currents with reduced ripple voltage at reduced ripple frequency. The charge pump system may include an array of charge pumps and a delay pipeline. The array of charge pumps may include a plurality of charge pumps. The delay pipeline may include a plurality of delay elements. The delay elements may respond to a global trigger signal to output a trigger signal to the array of charge pumps. Respective charge pumps may fire in response to the trigger signal. | 11-20-2014 |