Patent application number | Description | Published |
20080266940 | Air Cell Thermal Isolation for a Memory Array Formed of a Programmable Resistive Material - A memory device includes, a first electrode element, generally planar in form, having an inner contact surface. Then there is a cylindrical cap layer, spaced from the first electrode element, and a phase change element having contact surfaces in contact with the first electrode contact surface and the cap layer, in which the lateral dimension of the phase change element is less than that of the first electrode element and the cylindrical cap layer. A second electrode element extends through the cap layer to make contact with the phase change element. Side walls aligned with the cap layer, composed of dielectric fill material, extend between the first electrode elements and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell adjacent the phase change element. | 10-30-2008 |
20080304312 | RESISTANCE MEMORY WITH TUNGSTEN COMPOUND AND MANUFACTURING - Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element. | 12-11-2008 |
20090020740 | RESISTIVE MEMORY STRUCTURE WITH BUFFER LAYER - A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride. | 01-22-2009 |
20090032793 | Resistor Random Access Memory Structure Having a Defined Small Area of Electrical Contact - A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed. Also, methods for making the device include steps of constructing a dielectric form over a first electrode, and forming a conductive film over the dielectric form. | 02-05-2009 |
20090101883 | Method for manufacturing a resistor random access memory with a self-aligned air gap insulator - A memory device including a programmable resistive memory material is described along with methods for manufacturing the memory device. A memory device disclosed herein includes top and bottom electrodes and a multilayer stack disposed between the top and bottom electrodes. The multilayer stack includes a memory element comprising programmable resistive memory material and has a sidewall surface. An air gap is adjacent to the sidewall surface and self-aligned to the memory element. | 04-23-2009 |
20090130835 | METHOD OF MANUFACTURING INVERTED T-SHAPED FLOATING GATE MEMORY - A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T-shape, a U-shape, a trapezoid shape, or a double inverted T-shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T-shape, such that a top contour is a non-flat segment. | 05-21-2009 |
20090239358 | Memory Device Manufacturing Method - A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes. | 09-24-2009 |
20100054014 | HIGH DENSITY RESISTANCE BASED SEMICONDUCTOR DEVICE - Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Each memory cell comprises a diode and a plurality of memory elements each comprising one or more metal-oxygen compounds, the diode and the plurality of memory elements arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. | 03-04-2010 |
20100197119 | Resistor Random Access Memory Cell Device - A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film. | 08-05-2010 |
20100216279 | METHOD OF A MULTI-LEVEL CELL RESISTANCE RANDOM ACCESS MEMORY WITH METAL OXIDES - A method and structure of a bistable resistance random access memory comprise a plurality of programmable resistance random access memory cells where each programmable resistance random access memory cell includes multiple memory members for performing multiple bits for each memory cell. The bistable RRAM includes a first resistance random access member connected to a second resistance random access member through interconnect metal liners and metal oxide strips. The first resistance random access member has a first resistance value Ra, which is determined from the thickness of the first resistance random access member based on the deposition of the first resistance random access member. The second resistance random access member has a second resistance value Rb, which is determined from the thickness of the second resistance random access member based on the deposition of the second resistance random access member. | 08-26-2010 |
20100271878 | INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN - An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes. | 10-28-2010 |
20120037876 | Resistance Random Access Memory Structure for Enhanced Retention - A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other. | 02-16-2012 |
20140264615 | 3D MEMORY PROCESS AND STRUCTURES - A semiconductor device includes a substrate, a stack structure and a transistor. The substrate includes a first region and a second region. The stack structure is formed over the substrate in the first region. The transistor structure has a gate formed in the second region. A bottom portion of the gate structure is disposed at a height from the substrate that is less than a height between the substrate and a bottom portion of the stack structure. | 09-18-2014 |