Patent application number | Description | Published |
20080233700 | Methods of forming integrated circuitry - The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems. | 09-25-2008 |
20090180324 | Semiconductor Constructions, NAND Unit Cells, Methods Of Forming Semiconductor Constructions, And Methods Of Forming NAND Unit Cells - Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells. | 07-16-2009 |
20090206418 | Semiconductor Constructions - The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms. | 08-20-2009 |
20100112778 | NANOSCALE FLOATING GATE AND METHODS OF FORMATION - A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer. | 05-06-2010 |
20100176432 | Memory Cells, Methods Of Forming Dielectric Materials, And Methods Of Forming Memory Cells - Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material. | 07-15-2010 |
20110042754 | Gate Stacks and Semiconductor Constructions - The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms. | 02-24-2011 |
20110133268 | Memory Cells - Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones. | 06-09-2011 |
20110227142 | FORTIFICATION OF CHARGE-STORING MATERIAL IN HIGH-K DIELECTRIC ENVIRONMENTS AND RESULTING APPRATUSES - Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric. | 09-22-2011 |
20110297927 | OXIDE BASED MEMORY - Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode. | 12-08-2011 |
20120001248 | METHODS OF FORMING NANOSCALE FLOATING GATE - A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer. | 01-05-2012 |
20120069624 | REACTIVE METAL IMPLATED OXIDE BASED MEMORY - Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide. | 03-22-2012 |
20120074373 | Electronic Devices, Memory Devices and Memory Arrays - Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells. | 03-29-2012 |
20120267632 | SELECT DEVICES - Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms (Å) or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack. | 10-25-2012 |
20120292584 | RESISTIVE MEMORY CELL - Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions. | 11-22-2012 |
20130010525 | REACTIVE METAL IMPLATED OXIDE BASED MEMORY - Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide. | 01-10-2013 |
20130015422 | REACTIVE METAL IMPLATED OXIDE BASED MEMORY - Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide. | 01-17-2013 |
20130028016 | Memory Cells and Methods of Storing Information - Some embodiments include memory cells which have channel-supporting material, dielectric material over the channel-supporting material, carrier-trapping material over the dielectric material and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. Some embodiments include methods of storing information. A memory cell to is provided which has a channel-supporting material, a dielectric material over the channel-supporting material, a carrier-trapping material over the dielectric material, and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. It is determined if carriers are trapped in the carrier-trapping material to thereby ascertain a memory state of the memory cell. | 01-31-2013 |
20130069030 | RESISTIVE MEMORY CELL INCLUDING INTEGRATED SELECT DEVICE AND STORAGE ELEMENT - Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode. | 03-21-2013 |
20130070511 | SELECT DEVICES FOR MEMORY CELL APPLICATIONS - Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more memory cells comprise a a select device structure including a two terminal select device having a current-voltage (I-V) profile associated therewith, and a non-ohmic device in series with the two terminal select device. The combined two terminal select device and non-ohmic device provide a composite I-V profile of the select device structure that includes a modified characteristic as compared to the I-V profile, and the modified characteristic is based on at least one operating voltage associated with the memory cell. | 03-21-2013 |
20130099192 | Electronic Devices, Memory Devices and Memory Arrays - Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells. | 04-25-2013 |
20130109147 | Methods of Forming Metal Oxide and Memory Cells | 05-02-2013 |
20130153984 | Semiconductor Constructions, NAND Unit Cells, Methods of Forming Semiconductor Constructions, and Methods of Forming NAND Unit Cells - Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells. | 06-20-2013 |
20130187215 | METHODS OF FORMING NANOSCALE FLOATING GATE - A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer. | 07-25-2013 |
20130299893 | Memory Cells and Methods of Storing Information - Some embodiments include memory cells which have channel-supporting material, dielectric material over the channel-supporting material, carrier-trapping material over the dielectric material and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. Some embodiments include methods of storing information. A memory cell to is provided which has a channel-supporting material, a dielectric material over the channel-supporting material, a carrier-trapping material over the dielectric material, and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. It is determined if carriers are trapped in the carrier-trapping material to thereby ascertain a memory state of the memory cell. | 11-14-2013 |
20140034896 | Nonvolatile Memory Cells And Methods Of Forming Nonvolatile Memory Cells - A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned second current conductive material projecting elevationally outward from the first current conductive material. The second current conductive material is different in composition from the first current conductive material. A programmable region is formed over the first current conductive material and over the projecting second current conductive material of the first electrode. A second electrode is formed over the programmable region. In one embodiment, the programmable region is ion conductive material, and at least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Other method and structural aspects are disclosed. | 02-06-2014 |
20140097486 | Semiconductor Constructions, NAND Unit Cells, Methods Of Forming Semiconductor Constructions, And Methods Of Forming NAND Unit Cells - Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells. | 04-10-2014 |
20140106533 | MEMORY CELLS AND METHODS OF FORMING MEMORY CELLS - Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour. | 04-17-2014 |
20140106534 | Methods Of Forming A Programmable Region That Comprises A Multivalent Metal Oxide Portion And An Oxygen Containing Dielectric Portion - A method of forming a memory cell includes forming one of multivalent metal oxide material or oxygen-containing dielectric material over a first conductive structure. An outer surface of the multivalent metal oxide material or the oxygen-containing dielectric material is treated with an organic base. The other of the multivalent metal oxide material or oxygen-containing dielectric material is formed over the treated outer surface. A second conductive structure is formed over the other of the multivalent metal oxide material or oxygen-containing dielectric material. | 04-17-2014 |
20140112052 | Memory Programming Methods And Memory Systems - Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described. | 04-24-2014 |
20140153312 | MEMORY CELLS HAVING FERROELECTRIC MATERIALS - Memory cells having ferroelectric materials and methods of operating and forming the same are described herein. As an example, a memory cell can include a first electrode and a second electrode, and an ion source and a ferroelectric material formed between the first electrode and the second electrode, where the ferroelectric material serves to stabilize storage of ions transitioned from the ion source. | 06-05-2014 |
20140169066 | RESISTIVE MEMORY SENSING - The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal. | 06-19-2014 |
20140191182 | Memory Cells - Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state. | 07-10-2014 |
20140191229 | SEMICONDUCTOR STRUCTURE INCLUDING A ZIRCONIUM OXIDE MATERIAL - Semiconductor structures including a zirconium oxide material and methods of forming the same are described herein. As an example, a semiconductor structure can include a zirconium oxide material, a perovskite structure material, and a noble metal material formed between the zirconium oxide material and the perovskite structure material. | 07-10-2014 |
20140312291 | Nonvolatile Memory Cells And Methods Of Forming Nonvolatile Memory Cells - A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned second current conductive material projecting elevationally outward from the first current conductive material. The second current conductive material is different in composition from the first current conductive material. A programmable region is formed over the first current conductive material and over the projecting second current conductive material of the first electrode. A second electrode is formed over the programmable region. In one embodiment, the programmable region is ion conductive material, and at least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Other method and structural aspects are disclosed. | 10-23-2014 |
20140339624 | Charge-Retaining Transistor, Array Of Memory Cells, and Methods Of Forming A Charge-Retaining Transistor - A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. Islands of charge-trapping material are alongside the first semiconductor material. An oxidation-protective material is alongside the islands. Second semiconductor material is alongside the oxidation-protective material, and is of some different composition from that of the oxidation-protective material. Tunnel dielectric is alongside the charge-storage node. Channel material is alongside the tunnel dielectric. Additional embodiments, including methods, are disclosed. | 11-20-2014 |
20140346428 | MEMORY CELL STRUCTURES - The present disclosure includes memory cell structures and method of forming the same. One such method includes forming a memory cell includes forming, in a first direction, a select device stack including a select device formed between a first electrode and a second electrode; forming, in a second direction, a plurality of sacrificial material lines over the select device stack to form a via; forming a programmable material stack within the via; and removing the plurality of sacrificial material lines and etching through a portion of the select device stack to isolate the select device. | 11-27-2014 |
20140361239 | THREE DIMENSIONAL MEMORY ARRAY WITH SELECT DEVICE - Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines. | 12-11-2014 |
20140362634 | OXIDE BASED MEMORY - Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode. | 12-11-2014 |
20150044850 | RESISTIVE MEMORY CELL - Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions. | 02-12-2015 |
20150060751 | MEMORY CELLS WITH RECESSED ELECTRODE CONTACTS - Memory cells with recessed electrode contacts and methods of forming the same are provided. An example memory cell can include an electrode contact formed in a substrate. An upper surface of the electrode contact is recessed a distance relative to an upper surface of the substrate. A first portion of a memory element is formed on an upper surface of the electrode contact and the upper surface of the substrate. | 03-05-2015 |