Patent application number | Description | Published |
20140124949 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method of manufacturing the same. The method may, for example, comprise forming an interposer on a dummy substrate; forming a conductive pillar on the interposer; contacting the top of the interposer with at least one semiconductor die; encapsulating the conductive pillar and the at least one semiconductor die with an encapsulant; forming a redistribution layer that is electrically connected to the conductive pillar, on the semiconductor die; removing the dummy substrate from the interposer; attaching the interposer, which has the at least one semiconductor die in contact, to a substrate and testing the at least one semiconductor die; and contacting a stacked semiconductor device with the redistribution layer. | 05-08-2014 |
20140131856 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer. | 05-15-2014 |
20140131886 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device and a method of manufacturing the same. A carrier is removed after a first semiconductor die and a second semiconductor die are stacked on each other, and then a first encapsulant is formed, so that the carrier may be easily removed when compared to approaches in which a carrier is removed from a wafer having a thin thickness. | 05-15-2014 |
20140138817 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer. | 05-22-2014 |
20140147970 | SEMICONDUCTOR DEVICE USING EMC WAFER SUPPORT SYSTEM AND FABRICATING METHOD THEREOF - Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die. | 05-29-2014 |
20150014830 | SEMICONDUCTOR DEVICE UTILZING REDISTRIBUTION LAYERS TO COUPLE STACKED DIE - A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer. | 01-15-2015 |
20150021751 | SEMICONDUCTOR DEVICE WITH PLATED PILLARS AND LEADS - A semiconductor device with plated pillars and leads is disclosed and may include a semiconductor die comprising a conductive pillar, a conductive lead electrically coupled to the conductive pillar, a metal plating layer covering the conductive lead and conductive pillar, and an encapsulant material encapsulating the semiconductor die and at least a portion of the plating layer. The pillar, lead, and plating layer may comprise copper, for example. The plating layer may fill a gap between the pillar and the lead. A portion of the metal plating layer may, for example, comprise an external lead. The metal plating layer may cover a side surface of the pillar and a top surface, side surface, and at least a portion of a bottom surface of the lead. The metal plating layer may cover side and bottom surfaces of the pillar and top, side, and at least a portion of bottom surfaces of the conductive lead. | 01-22-2015 |
20150021767 | SEMICONDUCTOR DEVICE WITH PLATED CONDUCTIVE PILLAR COUPLING - A semiconductor device with plated conductive pillar coupling is disclosed and may include a semiconductor die comprising a conductive pillar formed on a bond pad on the die, a substrate comprising an insulating layer with conductive patterns formed on a first surface of the substrate and a second surface opposite to the first surface, and a plating layer electrically coupling the conductive pillar and the bond pad on the first surface of the die to the conductive pattern on the first surface of the substrate. The conductive pillar, the conductive patterns, and the plating layer may comprise copper. The plating layer may fill a void between the copper pillar and the conductive pattern on the first surface of the substrate. The substrate may comprise a rigid circuit board, a flexible circuit board, a ceramic substrate, a semiconductor die, or semiconductor wafer. | 01-22-2015 |
20150021791 | SEMICONDUCTOR DEVICE - Various aspects of the present disclosure provide a semiconductor device and a method for manufacturing thereof, which can facilitate stacking of semiconductor die while saving manufacturing cost. In an example embodiment, the semiconductor device may comprise a first semiconductor die, a second semiconductor die bonded to a top surface of the first semiconductor die, and a redistribution layer electrically connecting the first semiconductor die to the second semiconductor die, wherein the redistribution layer is formed to extend along surrounding side portions of the second semiconductor die. | 01-22-2015 |
20150041980 | Semiconductor Package with Reduced Thickness - A method for forming a reduced thickness semiconductor package is disclosed and may include providing a first die with an active layer, a through-silicon via (TSV), and a pattern and an under bump metal (UBM) in a dielectric layer on the active layer. A carrier may be bonded to the dielectric layer and the UBM. The first die may be thinned to expose the TSV. A bump pad may be formed on the exposed TSV and a second die may be bonded to the bump pad. The first die, the second die, and an outer surface of the dielectric layer may be encapsulated utilizing a first encapsulant. The carrier may be removed from the dielectric layer and the UBM, and a solder ball may be formed on the UBM. A groove may be formed through the dielectric layer and into the first die. | 02-12-2015 |
20150049421 | ELECTRONIC DEVICE PACKAGE STRUCTURE AND METHOD FABRICATING THE SAME - In one embodiment, an electronic device package structure includes an electronic die having conductive pads on one surface. The one surface is further attached to at least one lead. A conductive layer covers at least one conductive pad and at least portion of the lead thereby electrically connecting the lead to the conductive pad. | 02-19-2015 |
20150200179 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer. | 07-16-2015 |
20150206807 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise connection verification for a first one or more mounted components prior to additional assembly. | 07-23-2015 |
20150221573 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate. | 08-06-2015 |
20150221586 | SEMICONDUCTOR DEVICE WITH REDUCED THICKNESS - A semiconductor device with reduced thickness is disclosed and may include forming a back end of line (BEOL) comprising a redistribution layer on a dummy substrate. A first semiconductor die may be bonded to a first surface of the BEOL and a second semiconductor die may be bonded to the first semiconductor die. The first and second semiconductor dies may be electrically coupled to the BEOL. The first and second semiconductor dies and the BEOL may be encapsulated utilizing a first encapsulant. The dummy substrate may be removed thereby exposing a second surface of the BEOL opposite to the first surface. A solder ball may be placed on the exposed second surface of the BEOL. The second semiconductor may be stacked stepwise on the first semiconductor and may be flip-chip bonded. The semiconductor dies may be electrically coupled to the BEOL utilizing a lateral plating layer or conductive wires. | 08-06-2015 |
20150221601 | SEMICONDUCTOR DEVICE WITH REDISTRIBUTION LAYERS FORMED UTILIZING DUMMY SUBSTRATES - A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form. | 08-06-2015 |
20150262945 | Semiconductor Device Utilizing Redistribution Layers To Couple Stacked Die - A method for a semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include bonding a first semiconductor die to a second semiconductor die, the first semiconductor die having a first surface comprising bond pads, a second surface opposite the first surface that is bonded to a first surface of the second semiconductor die, and sloped sides surfaces between the first and second surfaces of the first semiconductor die, such that a cross-section of the first semiconductor die is trapezoidal in shape. A passivation layer may be formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die. A redistribution layer may be formed on the passivation layer formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die. | 09-17-2015 |
Patent application number | Description | Published |
20100142485 | METHOD FOR PERFORMING HANDOVER IN WIRELESS COMMUNICATION SYSTEM - A method for performing a handover by a user equipment from a serving base station to a target base station includes transmitting a random access preamble to the target base station, receiving a random access response in response to the random access preamble; after receiving the random access response, transmitting a handover confirm message for indicating completion of the handover between the user equipment and the target base station, and transmitting a packet data sequence number report message indicating packet data received from the serving base station in a process of performing the handover. Repeated transmission of downlink data or uplink data can be avoided during a handover procedure. | 06-10-2010 |
20100208779 | Transmitter for Reducing Channel Selectivity - A transmitter for reducing time selectivity and/or frequency selectivity in a wireless communication system includes a plurality of transmit antennas, a phase shifter which is disposed for each transmit antenna and is configured to shift a phase of data transmitted through the transmit antenna by a phase shift value, and a channel selectivity processor configured to obtain the phase shift value by using a channel phase value fed back from a receiver. | 08-19-2010 |
20110013613 | METHOD OF PERFORMING HARQ IN WIRELESS COMMUNICATION SYSTEM - A method of performing hybrid automatic repeat request (HARQ) in a wireless communication system is provided. The method includes receiving a system configuration signal, the system configuration signal comprising frame configuration information and HARQ delay information, receiving a downlink (DL) signal in a DL subframe and transmitting an acknowledgement (ACK)/not-acknowledgement (NACK) signal for the DL signal in a UL subframe. | 01-20-2011 |
20110128893 | RESOURCE ALLOCATION METHOD FOR BACKHAUL LINK AND ACCESS LINK IN A WIRELESS COMMUNICATION SYSTEM INCLUDING RELAY - A resource allocation method of a relay station in a wireless communication system employing the relay station is provided. The method includes: receiving information on a resource allocation pattern for an access link and a backhaul link of a first frequency band; and determining a resource allocation pattern for an access link and a backhaul link of a second frequency band on the basis of the resource allocation pattern of the first frequency band, wherein the first frequency band is any one of an uplink frequency band and a downlink frequency band, and the second frequency band is a remaining one of the uplink frequency band and the downlink frequency band. | 06-02-2011 |
20110194502 | METHOD FOR TRANSMITTING VOIP PACKET - A method for transmitting a voice over Internet protocol (VoIP) packet includes allocating a radio resource for VoIP packet transmission to a user, transitioning a VoIP service from a talk period, in which the VoIP packet is transmitted using the radio resource, to a silence period in which the VoIP packet is not transmitted, releasing the radio resource during the silence period, and transitioning the VoIP service to the talk period by reallocating the radio resource. Limited radio resources can be further effectively used. | 08-11-2011 |
20110223923 | Method and Apparatus for Releasing Blank Zone by Macro Base Station in Wireless Communication System - Provided are a method and an apparatus for releasing a blank zone by a macro base station in a wireless communication system. The macro base station: receives channel information from a macro terminal that is serviced therefrom; determines based on the channel information whether or not a downlink blank zone allocated to a resource zone of a femto bas station is released; and transmits downlink blank zone release information to the femto base station if the downlink blank zone is supposed to be released. The downlink blank zone is a resource zone which restricts the downlink transmission, among all the resource zones used by the femto base station. The channel information may be the information about the distance between the femto base station and the macro terminal. | 09-15-2011 |
Patent application number | Description | Published |
20080219572 | METHOD AND APPARATUS FOR MOTION COMPENSATION SUPPORTING MULTICODEC - Provided are a method and apparatus for compensating motion of a moving image. The method includes calculating a pixel value of a pixel located between pixels of a reference image corresponding to a current image based on pixel values of the pixels of the reference image by using at least one method from among a plurality of methods, such as a vertical linear filtering, a horizontal linear filtering, and a cubic filtering, of interpolating the pixels of the reference image according to codec information indicating one of a plurality of codecs, such as MPEG4, H.264/AVC, and VC1, and restoring the current image by adding motion compensation data, including the calculated pixel value, and a difference between the reference image and the current image. | 09-11-2008 |
20090175345 | Motion compensation method and apparatus - Provided is a motion compensation method and apparatus. The motion compensation method includes performing register setting for motion compensation of an m | 07-09-2009 |
20100146223 | Apparatus and method for data management - Provided is a data processing method that may transmit, from a host unit including at least one host to a tiling unit, an input parameter and first data, tile the first data using a predetermined block interleaving scheme to convert the first data to second data, and store the converted second data in a memory unit. The data processing method may transmit, from a host unit including at least one host to an inverse tiling unit, an input parameter and a request signal for first data, extract second data corresponding to the request signal from the memory unit to store at least one second data that is tiled using a predetermined block interleaving scheme, and may transmit, to the host unit, the first data that is converted by inverse tiling the second data. Here, the first data may be in a data structure of a sequential scanning scheme. | 06-10-2010 |
20100153645 | Cache control apparatus and method - A cache control apparatus and method are provided. The cache control apparatus may include a parameter input unit to receive a first parameter corresponding to a block-level cache in a main memory, a cache index extraction unit to extract a cache index from the first parameter, a cache tag extraction unit to extract a cache tag from the first parameter, and a comparison unit to determine whether a cache hit occurs using the cache index and the cache tag. | 06-17-2010 |
20110247006 | Apparatus and method of dynamically distributing load in multiple cores - Provided is an apparatus and method of dynamically distributing load occurring in multiple cores that may determine a corresponding core to perform functions constituting an application program, thereby enhancing the entire processing rate. | 10-06-2011 |
20120030382 | DIRECT MEMORY ACCESS DEVICE FOR MULTI-CORE SYSTEM AND OPERATING METHOD OF THE SAME - A Direct Memory Access (DMA) device for a multi-core system, and an operating method of the DMA device are provided. The DMA device includes a channel state determining unit to determine whether at least one channel among a source channel and a destination channel is available, the source channel being formed between a source core and the DMA device, and the destination channel being formed between a destination core and the DMA device, and a data transmission processing unit to process data of the source core to be transmitted to the destination core, when both the source channel and the destination channel are determined to be available. | 02-02-2012 |
20120155551 | APPARATUS AND METHOD FOR SEQUENTIALLY PARSING BITSTREAMS BASED ON REMOVAL OF EMULATION PREVENTION BYTE - An apparatus and method sequentially parses bitstreams based on a removal of an Emulation Prevention Byte (EPB). The apparatus and method may detect an EPB pattern from among sequentially input bitstreams, may store the bitstreams, may store a processed bitstream where the EPB pattern is removed, among the bitstreams, and may select an output of a register buffer based on an input of a buffer selection flag. | 06-21-2012 |
20130202048 | DEBLOCKING FILTERING APPARATUS AND METHOD BASED ON RASTER SCANNING - A deblocking filtering apparatus and method based on raster scanning is provided. The deblocking filtering apparatus may include a boundary determining unit to determine whether at least one of a vertical edge boundary and a horizontal edge boundary of a block corresponds to at least one of a coding unit (CU) boundary, a transform unit (TU) boundary, and a prediction unit (PU) boundary, a boundary strength (BS) computing unit to compute a BS value for at least one of the vertical edge boundary and the horizontal edge boundary when at least one of the vertical edge boundary and the horizontal edge boundary of the block corresponds to at least one of the CU boundary, the TU boundary, and the PU boundary as a result of the determining, and a filtering performing unit to perform deblocking filtering on at least one of the vertical edge boundary and the horizontal edge boundary. | 08-08-2013 |
20130215976 | ENCODING/DECODING APPARATUS AND METHOD FOR PARALLEL CORRECTION OF IN-LOOP PIXELS BASED ON MEASURED COMPLEXITY, USING VIDEO PARAMETER - An encoding/decoding apparatus and method for parallel correction of in-loop pixels based on complexity using a video parameter may include a complexity measuring unit to measure a complexity of an in-loop pixel correction process, using video codec parameter information, in a video codec, and a core allocating unit to evenly distribute jobs associated with the in-loop pixel correction process, using the measured complexity. | 08-22-2013 |
20130229292 | APPARATUS AND METHOD FOR DECODING - A decoding apparatus and method store at least one table including at least one code, receive at least one instruction signal, and extract a symbol value and a symbol length from the at least one table based on the at least one instruction signal. The decoding apparatus calculates a target suffix length that minimizes the size of a generated table and minimizes the size of a non-prefix length of the at least one code. | 09-05-2013 |
20130315318 | DOUBLE REGISTER ARRAY BUFFER FOR MOTION COMPENSATION - Provided are a method and apparatus for buffering image data for motion compensation. One of two buffers of a double register array buffer, i.e., a first buffer, is selected as a buffer in which data corresponding to a row of a block of an image is to be written and the other of the double register array buffer is selected as a buffer from which data corresponding to another row of the block is to be read, thereby speeding up motion compensation processing when compared with the use of a single register array buffer. | 11-28-2013 |
20140149714 | RECONFIGURABLE PROCESSOR FOR PARALLEL PROCESSING AND OPERATION METHOD OF THE RECONFIGURABLE PROCESSOR - A reconfigurable processor and an operation method of the reconfigurable processor may include: a status register configured to store a status value used to determine at least one execution mode in a processor; a parallel processing scheduler configured to schedule at least one of a very long instruction word (VLIW) logic and a coarse grained architecture (CGA) logic to be used based on the stored status value; a VLIW register configured to store processed data according to the VLIW logic; and a CGA register configured to store processed data according to the CGA logic. | 05-29-2014 |
20140286391 | SAMPLE ADAPTIVE OFFSET (SAO) PROCESSING APPARATUS REUSING INPUT BUFFER AND OPERATION METHOD OF THE SAO PROCESSING APPARATUS - A sample adaptive offset (SAO) processing apparatus reusing an input buffer and an operation method of the SAO processing apparatus may include a SAO parameter parser to parse SAO parameter information from a bitstream; a SAO parameter adjuster to extract SAO type information and offset information from the parsed SAO parameter information; and a filtering performer to perform filtering on the bitstream based on the SAO type information and the offset information. | 09-25-2014 |
20140286442 | APPARATUS AND METHOD FOR IN-LOOP FILTERING BASED ON LARGEST CODING UNIT FOR REDUCING EXTERNAL MEMORY ACCESS BANDWIDTH - An apparatus and method for in-loop filtering based on a largest coding unit (LCU) to reduce an external memory access bandwidth. An in-loop filter may include an external memory to store decoded frames, an internal memory to store pixels in use for deblocking filtering and sample adaptive offset filtering, a horizontal deblocking filter to perform deblocking filtering on input pixels in a horizontal direction with respect to vertical edge boundaries within an input area, a vertical deblocking filter to perform deblocking filtering in a vertical direction with respect to horizontal edge boundaries within the input area, and a sample adaptive offset filter to perform sample adaptive offset filtering. | 09-25-2014 |
Patent application number | Description | Published |
20140036728 | APPARATUS AND METHOD FOR CONTROLLING A BACKBONE NETWORK FOR A SENSOR NETWORK - The apparatus for controlling a backbone network according to the present invention comprises: a context-interpreting unit, which interprets the request for a service of a sensor node, and generates a session containing routing information; a sensor node registration unit, which stores sensor node information and routing information, and which provides routing information; a gateway, which transmits the service request using routing information, and which receives a response message; and a message-processing unit, which transmits the service request, and which provides the response message. | 02-06-2014 |
20150364632 | SOLAR CELL HAVING WAVELENGTH CONVERTING LAYER AND MANUFACTURING METHOD THEREOF - The present invention relates to a solar cell having a wavelength converting layer formed of a polysilazane and a manufacturing method thereof to allow for low temperature sintering, to protect a wavelength converter from oxidation, degradation, and whitening, and thereby improve efficiency of the solar cell. The present invention provides for the solar cell including the wavelength converting layer which is formed by applying a coating solution containing a solvent, a polysilazane, and a wavelength converter onto a cell and an outer surface or inside of the cell, and then curing, and a manufacturing method of. | 12-17-2015 |
20160097236 | PHOTOREACTIVE SMART WINDOW - Provided is a photoreactive smart window. The photoreactive smart window includes a liquid crystal layer of which light transmittance changes according to the presence of ultraviolet (UV) light and which is combined with a solar cell. The photoreactive smart window is in a transparent condition in the daytime when UV light is generated from the sun, and accordingly sunlight passing therethrough is converted into electric energy. Also, the photoreactive smart window is in an opaque condition in the evening and at night when no UV light is generated from the sun, and accordingly no curtains are necessary on the windows. | 04-07-2016 |
Patent application number | Description | Published |
20120149289 | COMPOSITION FOR CUTTING WHEEL AND CUTTING WHEEL BY USING THE SAME - Disclosed are a cutting wheel composition, and a cutting wheel using the cutting wheel composition. The disclosed composition includes 50 to 85 wt % of abrasive particles, 10 to 25 wt % of binder resin, and balance filler, wherein the binder resin includes a phenolic resin as a first binder resin; and at least one of a (bis)maleimide resin and a cyanate ester resin as a second binder resin. The composition includes at least one of the (bis)maleimide resin and the cyanate ester resin, as well the phenolic resin, as the binder resin, and thereby makes it possible to fabricate a cutting wheel having improved life characteristics through the improvement of heat-resistance and scratch-resistance. | 06-14-2012 |
20140336378 | NOVEL BENZAMIDE DERIVATIVE AND USE THEREOF - Disclosed are a novel benzamide derivative and pharmaceutical use thereof, and more particularly, a novel benzamide derivative having a structure of Formula 1 or pharmaceutically acceptable salts thereof, and a composition for prevention or treatment of pain or itching including the above material. The novel benzamide derivative and pharmaceutically acceptable salt thereof according to the present invention exhibit excellent pain-suppressive effect and, in particular, pain-suppressive effect in not only a neuropathic animal model but also other models such as a formalin model, and therefore, may be used in suppression of different pains such as nociceptive pain, chronic pain, etc. Further, since it was demonstrated that the present invention displays anti-pruritic efficacy even in an itching model, to which a mechanism and treatment concept established with respect to pain is applied, the present invention may also be effectively used in radical treatment of atopic dermatitis by applying the inventive product to an anti-pruritic composition in order to suppress an initial itching stage and treat symptoms thereof, thus preventing skin damage or inflammation after the scratching stage. | 11-13-2014 |
20150290181 | COMBINATION OF EFFECTIVE SUBSTANCES CAUSING SYNERGISTIC EFFECTS OF MULTIPLE TARGETING AND USE THEREOF - Disclosed are a combination of active components inducing synergistic effects of multi-targeting and a use thereof. More particularly, disclosed are a functional food composition, a cosmetic composition, a pain-suppressive composition, and a composition for treatment or prevention of pruritus or atopic dermatitis, which comprise as active components, two or more components selected from a group consisting of (a) a 5-hydroxytryptamine subtype 2 (5-HT2) receptor antagonist; (b) a P2X receptor antagonist; and (c) any one of a glycine receptor agonist, a glycine transporter (GlyT) antagonist, a gamma-aminobutyric acid (GABA) receptor agonist, and a GABA transporter 1 (GAT1) antagonist. The multi-targeting composite composition (specifically, natural substances composite composition) has synergistic effects, and thus a treatment using a combination of respective components may achieve increased biological effects, in which mechanisms targeted by respective components are involved. Thus, the multi-targeting composite composition may not only remarkably control pain but may also increase effects of: alleviating symptoms of skin diseases such as itching and atopic dermatitis; preventing or improving depression, refreshment, pore minimization, improving wrinkles, skin regeneration, skin health, recovery of skin condition, skin whitening, preventing or improving athlete's foot, recovery of scalp health and regeneration of scalp, promoting hair growth, preventing gray hair, and improving dental and periodontal diseases, etc. | 10-15-2015 |