Patent application number | Description | Published |
20080225599 | FLASH MEMORY DEVICE WITH REDUCED COUPLING EFFECT AMONG CELLS AND METHOD OF DRIVING THE SAME - Embodiments of the invention provide a flash memory device that can improve the reliability of a reading operation by minimizing a variation in the threshold voltage distribution that occurs due to coupling between cells, and a method of driving the flash memory device. In an embodiment of the invention, the method of driving the flash memory includes: performing an erasing operation on memory cells; after the performing the erasing operation, performing a post-programming operation to control a threshold voltage of the memory cells; and after performing the post-programming operation, performing a main programming operation on the memory cells, wherein the performing of the post-programming operation comprises increasing the threshold voltage of the memory cells in an erased state, thereby reducing a difference in the threshold voltage between the memory cells in the erased state and the memory cells in the programmed state. | 09-18-2008 |
20080235442 | FLASH MEMORY DEVICE CAPABLE OF IMPROVING READ PERFORMANCE - A flash memory device, related system ad method are disclosed. The memory device includes a memory cell array a page buffer receiving read data, wherein the page buffer includes a main register transferring read data to a cache register during an read operation, and a control logic block controlling operation of the page buffer during the read operation, such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register. | 09-25-2008 |
20080239809 | FLASH MEMORY DEVICE AND METHOD FOR PROVIDING INITIALIZATION DATA - A flash memory device includes a cell array and a decision unit. The cell array includes multiple regions corresponding to multiple input/output lines. Initialization data are repeatedly stored in each of the regions. The decision unit determines whether the stored data are valid based on values of bits of the stored data read from each region. | 10-02-2008 |
20080244339 | Read level control apparatuses and methods - Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate. | 10-02-2008 |
20080259690 | FLASH MEMORY DEVICE - A NAND flash memory device includes a high voltage switch and a bulk voltage supplying circuit. The high voltage switch is configured to transfer a word line voltage to selected word lines of selected memory cells. The bulk voltage supplying circuit is configured to provide a negative voltage to a bulk region of the high voltage switch in response to an operation mode. | 10-23-2008 |
20080273405 | Multi-bit programming device and method of multi-bit programming - A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells. | 11-06-2008 |
20080276149 | Error control code apparatuses and methods of using the same - An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data. | 11-06-2008 |
20080276150 | ERROR CONTROL CODE APPARATUSES AND METHODS OF USING THE SAME - An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose. | 11-06-2008 |
20080285340 | Apparatus for reading data and method using the same - Disclosed are an apparatus and a method for reading data. The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage. | 11-20-2008 |
20080291738 | METHODS AND CIRCUITS FOR GENERATING A HIGH VOLTAGE AND RELATED SEMICONDUCTOR MEMORY DEVICES - Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed. | 11-27-2008 |
20080310234 | NONVOLATILE MEMORY DEVICE AND METHODS OF PROGRAMMING AND READING THE SAME - A read method of a non-volatile memory device includes reading an initial threshold voltage value of an index cell from threshold voltage information cells that store information indicating the initial threshold voltage, determining a current threshold voltage value from the index cell, and comparing the initial threshold voltage value and the current threshold voltage value to calculate a shifted threshold voltage level of the index cell. A read voltage is changed by the shifted threshold voltage level to read user data using the changed read voltage. | 12-18-2008 |
20080316834 | BIAS CIRCUITS AND METHODS FOR ENHANCED RELIABILITY OF FLASH MEMORY DEVICE - A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit. | 12-25-2008 |
20090027971 | Apparatuses, computer program products and methods for reading data from memory cells - In reading data from a memory cell, a determining circuit determines whether a received voltage value is within at least one first voltage range through a one-time read operation using a semiconductor device that senses an output current corresponding to the received voltage value. The at least one first voltage range includes a first upper limit voltage value and a first lower limit voltage value. A data value of the memory cell is set as a first data value when the received voltage value is within the specific voltage range. | 01-29-2009 |
20090046510 | Apparatus and method for multi-bit programming - Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus may include: a first programming unit that stores data corresponding to a number of first bits in at least one first memory cell that may be connected to at least one first bit line; and a second programming unit that stores data corresponding to a number of second bits in at least one second memory cell that may be connected to at least one second bit line. Through this, it may be possible to improve data reliability and increase a number of bits to be stored in the entire memory cell. | 02-19-2009 |
20090067237 | MULTI-BIT DATA MEMORY SYSTEM AND READ OPERATION - Provided is a read operation for a N-bit data non-volatile memory system. The method includes determining in relation to data states of adjacent memory cells associated with a selected memory cell in the plurality of memory cells whether read data obtained from the selected memory cell requires compensation, and if the read data requires compensation, replacing the read data with compensated read data. | 03-12-2009 |
20090070656 | MEMORY SYSTEM WITH ERROR CORRECTION DECODER ARCHITECTURE HAVING REDUCED LATENCY AND INCREASED THROUGHPUT - A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory. | 03-12-2009 |
20090091990 | Apparatus and method of multi-bit programming - Disclosed are a multi-bit programming apparatus and a multi-bit programming method. The multi-bit programming apparatus may include a first control unit that may generates 2 | 04-09-2009 |
20090097314 | PAGE BUFFER AND MULTI-STATE NONVOLATILE MEMORY DEVICE INCLUDING THE SAME - According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode. | 04-16-2009 |
20090103359 | Apparatus and method of multi-bit programming - Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage. The multi-bit programming apparatus may generate better threshold voltage distributions in a multi-bit cell memory. | 04-23-2009 |
20090103360 | Multi-Bit Flash Memory Device and Program and Read Methods Thereof - The flash memory device of the present invention is configured to program a plurality of bits per unit cell, wherein a program condition of a selected bit is set according to whether a program for the most previous bit to the selected bit for programming is skipped or not skipped. As a result, an accurate programming and reading operation is possible even in case a program for a middle bit is skipped. | 04-23-2009 |
20090150751 | MEMORY SYSTEM THAT USES AN INTERLEAVING SCHEME AND A METHOD THEREOF - A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected with the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein the chip enable signal lines enable the plurality of memory devices independently. The controller sends a read command or a program command to one of the plurality of memory devices, and while the one of the plurality of memory devices is performing an internal read operation in response to the read command, the controller reads data from another one of the plurality of memory devices, or while the one of the plurality of memory devices is performing an internal program operation in response to the program command, the controller programs data to another one of the plurality of memory devices. | 06-11-2009 |
20090164710 | SEMICONDUCTOR MEMORY SYSTEM AND ACCESS METHOD THEREOF - A semiconductor memory system and access method thereof. The semiconductor memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores monitoring data in one or more of plural memory cells. The memory controller controls the nonvolatile memory. The memory controller detects the monitoring data and adjusts a bias voltage, which is provided to the plural memory cells, in accordance with a result of the detection. | 06-25-2009 |
20090196097 | Device for reading memory data and method using the same - Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage. | 08-06-2009 |
20090201729 | Memory device and memory device heat treatment method - A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the one or more heating devices based on operational information of the non-volatile memory device. Through this, it may be possible to improve an available period of the non-volatile memory device. | 08-13-2009 |
20090207671 | Memory data detecting apparatus and method for controlling reference voltage based on error in stored data - Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first voltage comparator to compare a threshold voltage of a memory cell with a first reference voltage, a first data determiner to determine a value of at least one data bit stored in the memory cell according to a result of the comparison, an error verifier to verify whether an error occurs in the determined value, a reference voltage determiner to determine a second reference voltage that is lower than the first reference voltage based on a result of the verification, and a second data determiner to re-determine the value of the data based on the determined second reference voltage. | 08-20-2009 |
20090210776 | Memory device and memory data reading method - Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead. | 08-20-2009 |
20090231914 | Memory devices and methods - Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit. | 09-17-2009 |
20090231917 | FLASH MEMORY DEVICE AND METHOD FOR PROGRAMMING FLASH MEMORY DEVICE HAVING LEAKAGE BIT LINES - Provided is a method for programming a flash memory device. The method includes receiving writing data, detecting leakage bit lines of the flash memory device, and updating the received writing data in order for data corresponding to the leakage bit lines to be modified as program-inhibit data. A programming operation is performed on the flash memory device after updating the writing data. | 09-17-2009 |
20090262582 | Method of Programming Flash Memory Device - Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage. | 10-22-2009 |
20090285022 | Memory programming method - A memory programming method may include identifying at least one of a plurality of memory cells with a threshold voltage to be changed based on a pattern of data to be programmed in the at least one of the plurality of memory cells, applying a program condition voltage to the at least one identified memory cell until the threshold voltage of the at least one identified memory cell is included in a first threshold voltage interval, to thereby adjust the threshold voltage of the at least one identified memory cell, and programming the data in the at least one identified memory cell with the adjusted threshold voltage. | 11-19-2009 |
20090296466 | Memory device and memory programming method - Provided are memory devices and memory programming methods. A memory device may include: a multi-bit cell array that includes a plurality of memory cells; a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage. | 12-03-2009 |
20090296486 | Memory device and memory programming method - Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell. | 12-03-2009 |
20090296494 | PAGE-BUFFER AND NON-VOLATILE SEMICONDUCTOR MEMORY INCLUDING PAGE BUFFER - In one aspect a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node. | 12-03-2009 |
20100067297 | BIAS CIRCUITS AND METHODS FOR ENHANCED RELIABILITY OF FLASH MEMORY DEVICE - A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit. | 03-18-2010 |
20100165742 | METHODS AND CIRCUITS FOR GENERATING A HIGH VOLTAGE AND RELATED SEMICONDUCTOR MEMORY DEVICES - Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed. | 07-01-2010 |
20100202204 | PAGE-BUFFER AND NON-VOLATILE SEMICONDUCTOR MEMORY INCLUDING PAGE BUFFER - In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node. | 08-12-2010 |
20110038207 | FLASH MEMORY DEVICE, PROGRAMMING AND READING METHODS PERFORMED IN THE SAME - The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through N | 02-17-2011 |
20110145663 | Read level control apparatuses and methods - Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate. | 06-16-2011 |
20110205817 | METHOD AND APPARATUS FOR MANAGING OPEN BLOCKS IN NONVOLATILE MEMORY DEVICE - A memory system comprises a multi-bit memory device and a memory controller that controls the multi-bit memory device. The memory system determines whether a requested program operation is a random program operation or a sequential program operation. Where the requested program operation is a random program operation, the memory controller controls the multi-bit memory device to perform operations according to a fine program close policy or a fine program open policy. | 08-25-2011 |
20110208903 | FLASH MEMORY DEVICE CAPABLE OF IMPROVING READ PERFORMANCE - A flash memory device, related system ad method are disclosed. The memory device includes a memory cell array a page buffer receiving read data, wherein the page buffer includes a main register transferring read data to a cache register during an read operation, and a control logic block controlling operation of the page buffer during the read operation, such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register. | 08-25-2011 |
20120039120 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE DEVICE, AND MEMORY SYSTEM - A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer. | 02-16-2012 |
20120047321 | Address Scheduling Methods For Non-Volatile Memory Devices With Three-Dimensional Memory Cell Arrays - At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where âkâ is 2 or a natural number greater than 2. | 02-23-2012 |
20120063235 | Memory Devices For Reducing Boosting Charge Leakage And Systems Including The Same - A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array. | 03-15-2012 |
20120307560 | PAGE-BUFFER AND NON-VOLATILE SEMICONDUCTOR MEMORY INCLUDING PAGE BUFFER - A non-volatile memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path. | 12-06-2012 |
20130279260 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE DEVICE, AND MEMORY SYSTEM - A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer. | 10-24-2013 |