Patent application number | Description | Published |
20090307437 | Multiport Memory Architecture, Devices and Systems Including the Same, and Methods of Using the Same - A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses. | 12-10-2009 |
20100103185 | SWITCH PIN MULTIPLEXING - An integrated circuit (IC) within an IC package, where the IC includes a memory control module and a timing module. The memory control module is configured to control read/write operations of a memory IC via N pins of the IC package, where N is an integer greater than 1. The memory IC is external to the IC package. The timing module is configured to control on/off timing of (N*M) light emitting diodes (LEDs) arranged in N columns and M rows connected to the N pins and M pins of the IC, respectively, where M is an integer greater than 1. The read/write operations utilize the N pins during a first period. The N*M LEDs receive data from the M pins and refresh signals from the N pins during a second period that is different than the first period. | 04-29-2010 |
20120076057 | Duplex Mismatch Detection - An apparatus including a port to transmit first frames and receive second frames over a communication channel, the port including a collision detect circuit and a duplex mismatch circuit. The collision detect circuit detects collisions on the communication channel between the first frames and the second frames. The duplex mismatch circuit declares a duplex mismatch when the communication channel was established without attempting auto-negotiation, the port is in a half-duplex mode, and the collision detect circuit detects a very late collision involving one of the first frames. The very late collision occurs after a predetermined amount of data has been transmitted in the one of the first frames. The duplex mismatch indicates that a full-duplex mode is used with respect to the second frames. | 03-29-2012 |
20120182999 | QUALITY OF SERVICE HALF-DUPLEX MEDIA ACCESS CONTROLLER - A network switch includes a transmitter and a controller. The transmitter is configured to selectively terminate transmission of a first frame from the network switch. The controller is configured to, in response to the transmitter terminating the transmission of the first frame, increment respective attempt counts for a first class of service associated with the first frame and all classes of service lower than the first class of service, determine whether any of the respective attempt counts is greater than a predetermined attempt threshold, and, in response to any of the respective attempt counts being greater than the predetermined attempt threshold, discard frames having the first class of service and frames having any of the classes of service lower than the first class of service. | 07-19-2012 |
20120230348 | DATA BLOCKING SYSTEMS FOR NON-ARBITRARY NETWORKS - A network device includes a memory with a first queue and a second queue. A timing module generates a first priority timing signal or a second priority timing signal based on a clock signal. The clock signal is shared between the network device and other network devices in a non-arbitrary network. The network device includes a deblocking shaper or a blocking shaper. The deblocking shaper (i) forwards first protected data from the first queue, and (ii) generates a deblocking signal based on a first frame signal and the first priority timing signal. The blocking shaper (i) forwards one of second protected data and unprotected data from the second queue, and (ii) generates a first blocking signal based on a second frame signal and the second priority timing signal. A selector module selects the first frame or the second frame based on the deblocking signal and the first blocking signal. | 09-13-2012 |
20130046886 | Controlling a Network Connection Status Indicator - This disclosure describes techniques for restricting activity of a status indicator if a received data unit is determined to be a protocol control unit that is selected for filtering. In one embodiment, a method is described that comprises receiving a data unit from a network, determining whether the received data unit is a protocol control unit, and restricting activity of a status indicator if the received data unit is determined to be the protocol control unit, or allowing activity of the status indicator if the received data unit is determined to be data other than the protocol control unit. | 02-21-2013 |
20130173950 | METHOD AND APPARATUS FOR COMMUNICATING TIME INFORMATION BETWEEN TIME AWARE DEVICES - According to one embodiment, an apparatus includes a first processing unit operating according to a first clock, a second processing unit operating according to a second clock running separately from the first clock, and a synchronization controller coupled to the first communication unit and the second communication unit. The synchronization controller is configured to (i) cause the first communication unit to generate a first indication of time at which the first processing unit transmits a signal to the second processing unit, according to the first clock, (ii) cause the second processing unit to generate a second indication of time at which the second processing unit receives the signal, according to the second clock, and (iii) determine an offset between the first clock and the second clock based on the first indication of time and the second indication of time. | 07-04-2013 |
20130215743 | NETWORK DEVICES WITH TIME AWARE MEDIUM ACCESS CONTROLLER - A network device includes a memory, a MAC module, a host control module, and a selector module. The memory stores frames and timestamps corresponding to the frames. The MAC module receives the frames and the timestamps and forwards the frames to a physical layer device. The MAC module includes queues that store the frames received from the memory, and shaping modules that receive the frames from the queues and spread data in the frames over time to generate blocking signals. The host control module transfers ownership of the frames to the MAC module. The host control module or the MAC module masks the transfer of the ownership of first frames including gating the first frames based on the timestamps to delay reception of the first frames in the queues. The selector module selects one of the blocking signals, and forwards the selected blocking signal to the physical layer device. | 08-22-2013 |
20140071823 | METHOD AND APPARATUS FOR TRANSMITTING PACKETS IN ACCORDANCE WITH IEEE 802.1 QBV - A network device including a plurality of queues configured to store respective frames of data having a priority level. The network device includes a shaper configured to transmit, during a first portion of a transmission interval, frames of data from a first one of the plurality of queues having a highest priority level, block frames of data from a second one of the plurality of queues during a blocking band extending from a first time prior to a start of the transmission interval to a second time indicating the start of the transmission interval, determine, based on the second time and a maximum frame size to be transmitted during the transmission interval, the second time, and selectively transmit, subsequent to the first time and prior to the second time, frames of data from the second one of the plurality queues based on the second time. | 03-13-2014 |
20140091728 | METHOD AND APPARATUS FOR MULTIPLEXING PINS OF AN INTEGRATED CIRCUIT - An integrated circuit within an integrated circuit package, including a configuration module and a timing module. The configuration module configures the integrated circuit using a configure operation performed via N pins of the integrated circuit package, where N is an integer greater than 1. The timing module is configured to control on/off timing of (N*M) light emitting diodes arranged in N columns and M rows connected to the N pins and M pins of the integrated circuit, respectively, where M is an integer greater than 1. During a first period, the configure operation utilizes the N pins. During a second period, the N*M light emitting diodes receive data from the M pins and refresh signals from the N pins. The second period is different than the first period. | 04-03-2014 |
20140215164 | Multiport Memory Architecture - The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data. The n-bit-wide words of data are then buffered as a k-word-long block of parallel data into a line of a multiline buffer as a block of k*n bits of data. The block of k*n bits of data is then transmitted to a multiport memory via a write bus effective to write the block of k*n bits of data to the multiport memory. | 07-31-2014 |