Patent application number | Description | Published |
20130043539 | INTERLAYER DIELECTRIC STRUCTURE AND METHOD MAKING THE SAME - The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process. | 02-21-2013 |
20130156940 | ADJUSTABLE NOZZLE FOR PLASMA DEPOSITION AND A METHOD OF CONTROLLING THE ADJUSTABLE NOZZLE - The description relates to an adjustable nozzle capable of pivoting about an axis of the nozzle and translating along the axis of the nozzle. A high density plasma chemical vapor deposition (HDP CVD) chamber houses a plurality of adjustable nozzles. A feedback control system includes a control unit coupled to the adjustable nozzle and the HDP CVD chamber to form a more uniform thickness profile of films deposited on a wafer in the HDP CVD chamber. | 06-20-2013 |
20130193350 | WAFER CURING APPARATUS HAVING IMPROVED SHRINKAGE - A wafer curing apparatus including a plate configured to pass ultraviolet light. The wafer curing apparatus further includes an antireflective coating on a light incident surface of the plate. The antireflective coating has an opening in a central portion thereof. A method of curing a wafer including emitting ultraviolet light from an ultraviolet light source. The method further includes transmitting the ultraviolet light through an ultraviolet transmissive plate having an antireflective coating thereon. The antireflective coating including an opening in a central portion thereof. The method further includes irradiating a wafer with the ultraviolet light transmitted through the ultraviolet transmissive plate. | 08-01-2013 |
20130228899 | MECHANISM OF PATTERNING A SEMICONDUCTOR DEVICE AND PRODUCT RESULTING THEREFROM - The description relates to a method of patterning a semiconductor device to create a through substrate via. The method produces a through substrate via having no photoresist material therein. An intermediate layer deposited over an interlayer dielectric prevents etching solutions from etching interlayer dielectric sidewalls to prevent peeling. The description relates to a semiconductor apparatus including a semiconductor substrate having a through substrate via therein. The semiconductor apparatus further includes an interlayer dielectric over the semiconductor substrate and an intermediate layer over semiconductor substrate and over sidewalls of the interlayer dielectric. | 09-05-2013 |
20130292791 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - In order to prevent formation of voids in STI film, after a second buried insulating layer is filled and planarized, a high density cap is formed embedded in the center region of the second buried insulating layer of the STI trench. The high density cap shields and protects the weaker center region of the second buried insulating layer of the STI trench from the subsequent processing steps and prevents formation of voids in the second buried insulating layer. | 11-07-2013 |
20140042553 | PROFILE PRE-SHAPING FOR REPLACEMENT POLY GATE INTERLAYER DIELECTRIC - Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed. | 02-13-2014 |
20140120706 | METHOD OF FORMING INTERLAYER DIELECTRIC FILM ABOVE METAL GATE OF SEMICONDUCTOR DEVICE - A method of forming an interlayer dielectric film above a metal gate of a metal oxide semiconductor device comprises forming a metal gate above a semiconductor substrate; and forming the interlayer dielectric film above the metal gate by reacting a silicon-containing compound as precursor and a reactant for oxidizing the silicon-containing compound. The silicon-containing compound has the formula: | 05-01-2014 |
20140231671 | GAS DELIVERY FOR UNIFORM FILM PROPERTIES AT UV CURING CHAMBER - A UV curing system includes an enclosure defining an interior, a UV radiation source disposed within the interior of the enclosure, and a first window disposed within the interior of the enclosure. The first window creates a barrier that separates the UV radiation source and a processing chamber. A second window is disposed within the interior of the enclosure at a distance from the first window to define a gas channel. The second window defines a plurality of openings such that the gas channel is in fluid communication with the processing chamber. A gas inlet conduit is in fluid communication with the gas channel and is configured to introduce a cooling gas into the gas channel. A gas outlet is in fluid communication with the processing chamber and is configured to remove gas from the processing chamber. | 08-21-2014 |
20140273537 | HIGH DENSITY PLASMA REACTOR WITH MULTIPLE TOP COILS - A plasma reactor includes an enclosure having a top and a bottom and defining a processing chamber. Inlets are formed in the enclosure for injecting process gas into the chamber. An outlet is formed in the enclosure for withdrawing gas from the chamber. A platform is positioned to support a wafer in the chamber above the bottom. A plurality of coils is positioned above the top of the chamber. Each coil is coupled to a radio frequency generator. | 09-18-2014 |
20140306294 | Gap Fill Self Planarization on Post EPI - The present disclosure relates to an integrated chip IC having transistors with structures separated by a flowable dielectric material, and a related method of formation. In some embodiments, an integrated chip has a semiconductor substrate and an embedded silicon germanium (SiGe) region extending as a positive relief from a location within the semiconductor substrate to a position above the semiconductor substrate. A first gate structure is located at a position that is separated from the embedded SiGe region by a first gap. A flowable dielectric material is disposed between the gate structure and the embedded SiGe region and a pre-metal dielectric (PMD) layer disposed above the flowable dielectric material. The flowable dielectric material provides for good gap fill capabilities that mitigate void formation during gap fill between the adjacent gate structures. | 10-16-2014 |
20140349471 | PROFILE PRE-SHAPING FOR REPLACEMENT POLY GATE INTERLAYER DIELECTRIC - Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed. | 11-27-2014 |
20140377961 | THIN FILM DEPOSITION APPARATUS WITH MULTI CHAMBER DESIGN AND FILM DEPOSITION METHODS - A multi chamber thin film deposition apparatus and a method for depositing films, is provided. Each chamber includes a three dimensional gas delivery system including process gases being delivered downwardly toward the substrate and laterally toward the substrate. A pumping system includes an exhaust port in each chamber that is centrally positioned underneath the substrate being processed and therefore the gas flow around all portions of the edge of the substrate are equally spaced from the exhaust port thereby creating a uniform gas flow profile which results in film thickness uniformity of films deposited on both the front and back surfaces of the substrate. The deposited films demonstrate uniform thickness on the front and back of the substrate and extend inwardly to a uniform distance on the periphery of the backside of the substrate. | 12-25-2014 |