Patent application number | Description | Published |
20090327986 | GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT WITH TIMING EXCEPTION PATHS - Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression. | 12-31-2009 |
20100191679 | METHOD AND APPARATUS FOR CONSTRUCTING A CANONICAL REPRESENTATION - Some embodiments provide systems and techniques to facilitate construction of a canonical representation (CR) which represents a logical combination of a set of logical functions. During operation, the system can receive a CR-size limit. Next, the system can construct a set of CRs based on the set of logical functions, wherein each CR in the set of CRs represents a logical function in the set of logical functions. The system can then combine a subset of the set of CRs to obtain a combined CR. Next, the system can identify a problematic CR which when combined with the combined CR causes the CR-size limit to be exceeded. The system can then report the problematic CR and/or a logical function associated with the problematic CR to a user, thereby helping the user to identify an error in the set of logical functions. | 07-29-2010 |
20100275169 | ADAPTIVE STATE-TO-SYMBOLIC TRANSFORMATION IN A CANONICAL REPRESENTATION - Some embodiments provide a system for adaptively performing state-to-symbolic transformation in a canonical representation which is used for generating random stimulus for a constrained-random simulation. The system can construct a canonical representation for a set of constraints using the set of random variables and the subset of the state variables in the constraints. Next, the system can use the canonical representation to generate random stimulus for the constrained-random simulation, and monitor parameters associated with the constrained-random simulation. Next, the system can add state variables to or remove state variables from the canonical representation based at least on the monitored parameters. The system can then use the modified canonical representation which has a different set of state variables to generate random stimulus for the constrained-random simulation. | 10-28-2010 |
20120136635 | METHOD AND APPARATUS FOR OPTIMIZING CONSTRAINT SOLVING THROUGH CONSTRAINT REWRITING AND DECISION REORDERING - Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints. | 05-31-2012 |
20120227022 | Technique For Honoring Multi-Cycle Path Semantics In RTL Simulation - An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of magnitude faster than gate level simulation. Moreover, design bugs associated with multi-cycle paths are more easily corrected during RTL simulation compared to waiting until the gate level simulation. | 09-06-2012 |
20120253754 | METHOD AND APPARATUS FOR IDENTIFYING INCONSISTENT CONSTRAINTS - Methods and apparatuses are described for identifying inconsistent constraints. During operation, a system can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. If an inconsistency or conflict is detected while solving the set of constraints, the system can identify a phase in a series of phases of the constraint solver where the inconsistency was detected. The system can then try to solve different subsets of the set of constraints to identify smaller subsets of the set of constraints that contain the inconsistency. When the system tries to solve a subset of the set of constraints, the system can determine whether or not an inconsistency is detected in the identified phase while solving the subset of the set of constraints. Next, the system can report the smallest subset of inconsistent constraints that was found to a user. | 10-04-2012 |
20120278675 | METHOD AND APPARATUS FOR PERFORMING IMPLICATION AND DECISION MAKING USING MULTIPLE VALUE SYSTEMS DURING CONSTRAINT SOLVING - Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. An embodiment can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. Next, the embodiment can generate a circuit model based on the set of constraints, wherein assignable values for at least one node in the circuit model are represented in multiple value systems. The embodiment can then assign random values to the set of random variables based on the circuit model. | 11-01-2012 |
20140067356 | INFORMATION THEORETIC CACHING FOR DYNAMIC PROBLEM GENERATION IN CONSTRAINT SOLVING - Computer-implemented techniques are disclosed for verifying circuit designs using dynamic problem generation. A device under test (DUT) is modeled as part of a test bench where the test bench is a random process. A set of constraints is solved to generate stimuli for the DUT. Problem generation is repeated numerous times throughout a verification process with problems and sub-problems being generated and solved. When a problem is solved, the problem structure can be stored in a cache. The storage can be based on entropy of variables used in the problem. The problem storage cache can be searched for previously stored problems which match a current problem. By retrieving a problem structure from cache, the computational burden is reduced during verification. Problems can be multi-phase problems with storage and retrieval of problem structures based on the phase level. Caching can be accomplished using an information theoretic approach. | 03-06-2014 |
20140068533 | INFORMATION THEORETIC SUBGRAPH CACHING - Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be stored in a cache. The storage can be based on entropy of variables used in the graph and subgraph problems. The subgraph problem storage cache can be searched for previously stored problems which match another problem in need of a solution. By retrieving subproblem variables, values, and information from the cache, the computational overhead of circuit design verification is reduced as problems are reused. Caching can be accomplished using an information theoretic approach. | 03-06-2014 |
20140282316 | SOLVING MULTIPLICATION CONSTRAINTS BY FACTORIZATION - A design description for verification includes a set of constraints on random variables within the design description. The set of constraints includes at least one multiplication constraint involving at least two random variables. A computer-based tool obtains designs and analyzes the design description to find the set of constraints and identify the multiplication constraint. The computer-based tool then performs factorization to solve for the multiplication constraint and to determine a set of potentially valid factoring values for the random variables used in the multiplication constraint. The design problem is then solved by the computer-based tool using the factoring values. If two multiplication constraints involve a common variable, the factorization finds a set of common factoring values between the two multiplication constraints to use for the common variable. | 09-18-2014 |
20140282343 | PRIORITIZED SOFT CONSTRAINT SOLVING - A design problem can include a mixture of hard constraints and soft constraints. The soft constraints can be prioritized and the design problem solved. One or more soft constraints may not be honored in the midst of the solving of the design problem. Debugging can be performed and the unsatisfied soft constraints identified. Root-cause analysis can evaluate the challenges within the design problem which caused soft constraints not to be honored. | 09-18-2014 |
20150067622 | DEVELOPMENT AND DEBUG ENVIRONMENT IN A CONSTRAINED RANDOM VERIFICATION - A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage. | 03-05-2015 |