Patent application number | Description | Published |
20130002348 | AMPLIFIER WITH IMPROVED NOISE REDUCTION - An amplifier with improved noise reduction is disclosed. In one implementation, an amplifier is provided that includes a main output stage configured to output an amplified signal at a main output terminal, a secondary output stage configured to output a copy of the amplified signal at a secondary output terminal, and a signal coupler configured to provide a variable resistance coupling between the secondary output terminal and the main output terminal to reduce noise at the main output terminal. | 01-03-2013 |
20130002359 | AMPLIFIER WITH HIGH POWER SUPPLY NOISE REJECTION - An amplifier with high power supply rejection is disclosed. In an exemplary implementation, an amplifier includes a first stage configured to receive a signal to be amplified, a second stage comprising an input transistor coupled to the first stage, and further comprising at least one additional transistor, and a voltage regulator configured to received a first supply voltage and generate a regulated supply voltage, the first supply voltage coupled to the at least one additional transistor, the regulated supply voltage coupled to the first stage and the input transistor of the second stage to improve power supply noise rejection of the apparatus. | 01-03-2013 |
20130156230 | WAVEFORM SHAPING FOR AUDIO AMPLIFIERS - Techniques for applying waveform shaping to DC-to-DC level transitions in an audio amplifier. In an aspect, a waveform shaping block may utilize a non-linear shaping waveform such as a Gaussian waveform, raised-cosine waveform, root-raised cosine waveform, etc., to shape the transition between two DC levels in an audio amplifier output. The waveform shaping techniques may be utilized, e.g., during power-up or power-down of the amplifier, or in an impedance measurement mode, to reduce audio artifacts associated with the transition while minimizing overall transition time. | 06-20-2013 |
20130257398 | SYSTEM AND METHOD FOR SUPPRESSION OF PEAKING IN AN EXTERNAL LC FILTER OF A BUCK REGULATOR - Disclosed are systems and methods for suppressing voltage peaking in a buck regulator. In one aspect, a buck regulator comprises: a pulse-width modulator (PWM) that generates a pulsed signal; a switch operable to selectively connect the regulator to a DC power supply in response to the pulsed signal and output a pulsed output DC signal; a filter for filtering out high frequency noise from the pulsed output DC signal and generating a regulated output signal; an integrator for comparing the pulsed output DC signal with a reference voltage signal and generating an error signal for input to the PWM; a subtractor operable to subtract the reference voltage signal from the filtered output signal to generate an error feedback signal; and an adder operable to add the error feedback signal to the error signal for input to the pulse-width modulator in order to suppress voltage peaks in the filtered output signal. | 10-03-2013 |
20130285751 | ENHANCED PULSE FREQUENCY MODULATION (PFM) CONTROL MODE FOR SWITCHING REGULATORS - A variable supply rail generator is described. The variable supply rail generator includes a regulator configured to use an estimated load current for a power amplifier to optimize efficiency. The variable supply rail generator also includes a power amplifier controller. The power amplifier controller provides the estimated load current to the regulator. | 10-31-2013 |
20140028397 | LOW VOLTAGE MULTI-STAGE AMPLIFIER - A low voltage multi-stage amplifier is described. The low voltage multi-stage amplifier includes one or more prior stages. The low voltage multi-stage amplifier also includes a supply stage. The low voltage multi-stage amplifier further includes an output stage that operates with a supply voltage as low as a sum of a threshold voltage of a first transistor in the output stage and a saturation voltage of a second transistor of the supply stage. The supply stage supplies the output stage. | 01-30-2014 |
20140103897 | GLITCH SUPPRESSION IN DC-TO-DC POWER CONVERSION - Exemplary embodiments are directed to devices and method for operating a charge pump. A method may include activating a first switch coupled between a capacitor and a ground voltage over a first period of a charging phase. The first period may coincide with a non-overlapping time between the charging phase and an output phase. The method may also include activating a second switch coupled between the capacitor and an input voltage over a second period of the charging phase, wherein the first period begins prior to the second period. Further, the method may include deactivating the second switch over a third period of the charging phase and deactivating the first switch over a fourth period of the charging phase, wherein the third period begins prior to the fourth period. | 04-17-2014 |
20140167860 | MULTI-STAGE AMPLIFIER - Exemplary embodiments are directed to operating a multi-stage amplifier with low-voltage supply voltages. A multi-stage amplifier may include a first path of an amplifier output stage configured to convey an output signal if a first supply voltage is greater than a threshold voltage. The multi-stage amplifier may also include a second path of the amplifier output stage configured to convey the output signal if the first supply voltage is less than or equal to the threshold voltage. | 06-19-2014 |
20140232362 | METHOD AND APPARATUS FOR IMPROVING DEVICE RELIABILITY USING ESTIMATED CURRENT IN A DYNAMIC PROGRAMMABLE SWITCHER DRIVER - A method and apparatus for a dynamic programmable switcher driver using estimated current for device reliability is provided. The method adjusts a rate of closure of an electronic switch and begins when the load current of the Buck regulator is estimated. This estimated current flow is then compared with a predetermined threshold. If the estimated current flow is greater than the predetermined threshold then the rate of closure of the electronic switch is decreased. If the estimated current flow is less than the predetermined threshold then the rate of closure of the switch is increased. An apparatus for adjusting a rate of closure of an electronic switch is also provided. The apparatus includes: an adjustable p-driver having an internal register value; an adjustable n-driver having an internal register value; a positive switch connected to the adjustable p-driver; and a negative switch connected to the adjustable n-driver. | 08-21-2014 |
20140232457 | FAST, LOW POWER COMPARATOR WITH DYNAMIC BIAS BACKGROUND - A comparator circuit comprising an operational amplifier configured to compare a difference between a switching voltage and a reference voltage, and a dynamically adjustable bias current generator coupled to the operational amplifier. A method of conserving power in a comparator circuit includes estimating a switching regulator load current value, communicating the value to a current bias generator, enabling the bias generator with a signal from a switching regulator PFM logic circuit, and establishing a bias current at an operational amplifier of the comparator circuit on the basis of the enabling. | 08-21-2014 |
20140253180 | CHARGE PUMP POWER SAVINGS - Exemplary embodiments are directed to systems, devices, methods, and computer-readable media for reducing static and dynamic power consumption of a charge pump. In one embodiment, a device may include a plurality of switches, each switch of the plurality having a gate coupled to a dedicated driver of a plurality of drivers. The device may further include at least one clamp switch coupled to at least one driver of the plurality of drivers and configured to adjust a rail voltage of the at least one driver if an input voltage is greater than a threshold voltage. In another embodiment, the device may include a plurality of multiplexers, each multiplexer of the plurality of multiplexers coupled to a portion of an associated switch of the plurality of switches and configured to disable the portion of the associated switch if a clock frequency of the charge pump is below a threshold frequency. | 09-11-2014 |
20150296300 | FM FILTERING FOR CLASS-G/H HEADPHONES - A radio frequency filtering circuit for audio headphones includes a switching power supply, audio amplifier section, one or more outputs from the audio amplifier section to one or more corresponding channels of the audio headphones, one or more L-C low pass filters arranged between the switching power supply and the audio amplifier section, and one or more L-C low pass filters arranged between the audio amplifier section and the one or more corresponding channels of the audio headphones. A method of filtering radio frequency signals for audio headphones includes providing an input voltage from a switching power supply section of a filtering circuit, passing the input voltage through an L-C low pass filter arranged between the switching power supply section and an audio amplifier section, and passing an output of the audio amplifier section through a second L-C low pass filter arranged between the audio amplifier section and an audio output to the headphones. | 10-15-2015 |
20150381120 | SLEW RATE CONTROL BOOST CIRCUITS AND METHODS - The present disclosure amplifier circuits and methods having boosted slew rates. In one embodiment, an amplifier circuit comprises an output stage comprising a first output transistor, the first output transistor comprising a gate, a source, and a drain, wherein the gate receives a signal to be amplified. A bias circuit biases the gate of the first output transistor. A damping circuit is coupled the gate of the first output transistor and is configured to produce a high impedance at low frequencies and a low impedance at high frequencies. The damping circuit includes a current limit circuit to limit current to the gate of the first output transistor when a voltage on the gate of the first output transistor decreases in response to the signal. | 12-31-2015 |
20150381161 | GLITCH SUPPRESSION IN AN AMPLIFIER - A driver circuit includes detectors responsive to the operating region that a driven switch is operating in. The driver circuit is operative to drive the gate of the driven switch at a speed responsive to the output of the detectors. | 12-31-2015 |