Deinlein
John J. Deinlein, Odenton, MD US
Patent application number | Description | Published |
---|---|---|
20090183251 | INTEGRATED INFORMATION MANAGEMENT SYSTEM AND METHOD - Embodiments of present invention provide for an integrated information management system. The system comprises a set of predetermined applications related to managing information of a government program. The system also comprises a web portal that renders a set of web pages as a virtual workspace. The web portal interoperates with the set of predetermined applications using a plurality of portlets. At least one of the plurality of portlets implementing an application of the set of predetermined applications that is external to the web portal and at least one of the plurality portlets implementing an application of the set of predetermined applications that is local to the web portal. | 07-16-2009 |
Justin Deinlein, Portland, OR US
Patent application number | Description | Published |
---|---|---|
20140189315 | Copy-On-Write Buffer For Restoring Program Code From A Speculative Region To A Non-Speculative Region - An apparatus is described having an out-of-order instruction execution pipeline. The out-of-order execution pipeline has a first circuit and a second circuit. The first circuit is to hold a pointer to physical storage space where information is kept that cannot yet be confirmed as being free of potential dependencies on the information. The second circuit is to hold the pointer if the pointer existed in the first circuit when a non speculative region of program code ended and upon retirement of a following speculative overwriter instruction originally coded to overwrite the information. | 07-03-2014 |
Justin M. Deinlein, Portand, OR US
Patent application number | Description | Published |
---|---|---|
20140189306 | ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION - An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled. | 07-03-2014 |