Patent application number | Description | Published |
20080243946 | Storage system and data recovery method - Proposed are a storage system and a data recovery method capable of guaranteeing data recovery processing at a service level sought by a user. This storage system and data recovery method uses one or more data recovery candidate points and specifies a section containing the journal and the replication of write data, checks a redundancy relation of a write range in the volume of write data written from host into the volume contained in the journal regarding one or more the journals in the section, and executes redundancy elimination processing of merging a plurality of the replications of write data or a plurality of the journals into a single replication of write data or a single journal based on the check result. | 10-02-2008 |
20080263190 | STORAGE SYSTEM - A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV. | 10-23-2008 |
20090198942 | STORAGE SYSTEM PROVIDED WITH A PLURALITY OF CONTROLLER MODULES - A plurality of global LDEV managed by a plurality of controller modules are provided above local LDEV under the control of each controller module. Each global LDEV is correlated to any of the plurality of local LDEV. The controller modules judge whether or not a local LDEV correlated to a global LDEV specified by an I/O request received from a host device or a first other controller module is a management target itself, and if the result of that judgment is affirmative, the controller modules access the local LDEV correlated to the specified global LDEV, while if the result of the judgment is negative, the controller modules transfer the received I/O request to a second other controller module. | 08-06-2009 |
20090254695 | STORAGE SYSTEM COMPRISING PLURALITY OF STORAGE SYSTEM MODULES - A plurality of modules ( | 10-08-2009 |
20090276661 | STORAGE SYSTEM CREATING A RECOVERY REQUEST POINT ENABLING EXECUTION OF A RECOVERY - A switch connected to a network system including a computer and a storage apparatus: controlling read/write request from the computer to the storage apparatus and controlling to store journal data in the storage apparatus; wherein the storage apparatus includes a first storage area for storing data to be used by the computer and a second storage area for storing journal data including write data and first update log information corresponding to the write data when there is a write request from the computer for writing data in the first storage area; wherein when the switch detects an event of status change related to the network system, the switch marks a first point of time corresponding to the event as a recovery request point, and creates second update log information corresponding to the recovery request point. | 11-05-2009 |
20100146232 | STORAGE SYSTEM, REMOTE COPY AND MANAGEMENT METHOD THEREFOR - A copy source storage controller received write data added with a time and issued from a host computer transfers the write data with the time to a copy destination storage controller. If there are a plurality of copy destination storage controllers, a representative copy destination storage controller compares times of write data copied to the plurality of copy destination storage controllers, and writes the write data in copy destination logical volumes in the sequential order of time. The representative copy destination storage controller judges that integrity of the write data is established, if a communication procedure is established with the copy destination storage controller and if the statuses of the copy source/destination logical volumes are coincident. In remote copy which guarantees integrity of write data and traverses a plurality of storage controllers, it is possible to judge at an optional time point whether integrity of write data can be guaranteed. | 06-10-2010 |
20110138085 | STORAGE SYSTEM - A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV. | 06-09-2011 |
20110145532 | STORAGE SYSTEM AND PROCESSING EFFICIENCY IMPROVING METHOD OF STORAGE SYSTEM - A storage system | 06-16-2011 |
20110219189 | STORAGE SYSTEM AND REMOTE COPY CONTROL METHOD FOR STORAGE SYSTEM - A storage system maintains consistency of the stored contents between volumes even when a plurality of remote copying operations are executed asynchronously. A plurality of primary storage control devices and a plurality of secondary storage control devices are connected by a plurality of paths, and remote copying is performed asynchronously between respective first volumes and second volumes. Write data transferred from the primary storage control device to the secondary storage control device is held in a write data storage portion. Update order information, including write times and sequential numbers, is managed by update order information management portions. An update control portion collects update order information from each update order information management portion, determines the time at which update of each second volume is possible, and notifies each-update portion. By this means, the stored contents of each second volume can be updated up to the time at which update is possible. | 09-08-2011 |
20110302382 | STORAGE SYSTEM, REMOTE COPY AND MANAGEMENT METHOD THEREFOR - A copy source storage controller received write data added with a time and issued from a host computer transfers the write data with the time to a copy destination storage controller. If there are a plurality of copy destination storage controllers, a representative copy destination storage controller compares times of write data copied to the plurality of copy destination storage controllers, and writes the write data in copy destination logical volumes in the sequential order of time. The representative copy destination storage controller judges that integrity of the write data is established, if a communication procedure is established with the copy destination storage controller and if the statuses of the copy source/destination logical volumes are coincident. In remote copy which guarantees integrity of write data and traverses a plurality of storage controllers, it is possible to judge at an optional time point whether integrity of write data can be guaranteed. | 12-08-2011 |
20120131287 | STORAGE CONTROL APPARATUS AND LOGICAL VOLUME SIZE SETTING METHOD - The present invention efficiently changes a volume size while maintaining a copy pair as-is. A PVOL and a SVOL # | 05-24-2012 |
20120159012 | STORAGE SYSTEM - A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV. | 06-21-2012 |
20120246429 | STORAGE SYSTEM AND REMOTE COPY CONTROL METHOD FOR STORAGE SYSTEM - A storage system for managing a plurality of asynchronous remote copy proceedings between a plurality of first storage control devices and a plurality of second storage control devices, wherein each of a plurality of second storage control devices stores one or more update data corresponding to one or more update data related information including the same update reflection time information with the one that is received or older update reflection time information than this in a one or more second logical volume and changes status of the one or more second logical volumes to suspend status. | 09-27-2012 |
20120311602 | STORAGE APPARATUS AND STORAGE APPARATUS MANAGEMENT METHOD - The overall processing function of a storage apparatus is improved by suitably migrating ownership. | 12-06-2012 |
20120311603 | STORAGE APPARATUS AND STORAGE APPARATUS MANAGEMENT METHOD - The overall processing performance of a storage apparatus is improved by migrating MPPK ownership with suitable timing. | 12-06-2012 |
20130036286 | FIRST STORAGE CONTROL APPARATUS AND FIRST STORAGE CONTROL APPARATUS CONTROL METHOD - The present invention creates a pool comprising tiers corresponding to the performance of logical volumes. | 02-07-2013 |
20130091328 | STORAGE SYSTEM - A storage system in an embodiment of this invention comprises a non-volatile storage area for storing write data from a host, a cache area capable of temporarily storing the write data before storing the write data in the non-volatile storage area, and a controller that determines whether to store the write data in the cache area or to store the write data in the non-volatile storage area without storing the write data in the cache area, and stores the write data in the determined area. | 04-11-2013 |
20130111127 | STORAGE SYSTEM AND DATA PROCESSING METHOD IN STORAGE SYSTEM | 05-02-2013 |
20130132617 | STORAGE SYSTEM - A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV. | 05-23-2013 |
20130246710 | STORAGE SYSTEM AND DATA MANAGEMENT METHOD - A storage system is provided with a plurality of physical storage devices, a cache memory, a control device that is coupled to the plurality of physical storage devices and the cache memory, and a buffer part. The buffer part is a storage region that is formed by using at least a part of a storage region of the plurality of physical storage devices and that is configured to temporarily store at least one target data element that is to be transmitted to a predetermined target. The control device stores a target data element into a cache region that has been allocated to a buffer region (that is a part of the cache memory and that is a storage region of a write destination of the target data element for the buffer part). The control device transmits the target data element from the cache memory. In the case in which a new target data element is generated, the control device executes a control in such a manner that the new target data element has a high tendency to be stored for a buffer region in which the transmitted target data element has been stored and to which a cache region has been allocated. | 09-19-2013 |
20130305003 | STORAGE APPARATUS AND DATA MANAGEMENT METHOD - The present invention provides high-speed copying of a compressed data volume. | 11-14-2013 |
20140208009 | STORAGE SYSTEM - A storage system in an embodiment of this invention comprises a non-volatile storage area for storing write data from a host, a cache area capable of temporarily storing the write data before storing the write data in the non-volatile storage area, and a controller that determines whether to store the write data in the cache area or to store the write data in the non-volatile storage area without storing the write data in the cache area, and stores the write data in the determined area. | 07-24-2014 |
Patent application number | Description | Published |
20090027285 | ANTENNA DEVICE AND RADIO COMMUNICATION SYSTEM - An antenna device includes: a substrate; first and a second antenna units which are wound coaxially on a surface of the substrate, and include a plurality of antenna elements; and a feeder which feeds power only to the first antenna unit. A separation distance between the antenna elements in each of the first and second antenna units is substantially the same. | 01-29-2009 |
20110115607 | TRANSMITTING / RECEIVING ANTENNA AND TRANSMITTER / RECEIVER DEVICE USING THE SAME - The present invention is concerned with a transmitting/receiving antenna, which includes a dielectric board, a driven loop antenna provided to the dielectric board, transmit processing portion connection terminals connected to the driven loop antenna, a transmitting/receiving loop antenna arranged in close vicinity to the driven loop antenna in a non-contact state, a resonance capacitor connected to both ends of the transmitting/receiving loop antenna, and receive processing portion connection terminals connected to the transmitting/receiving loop antenna. The driven loop antenna is constructed to have a loop wound in a single turn, and the transmitting/receiving loop antenna is constructed to have a loop wound in plural turns. According to this configuration, a wider frequency band of the frequency characteristic and a reduction of the power consumption can be achieved. | 05-19-2011 |
20120119965 | TRANSMISSION/RECEPTION ANTENNA AND TRANSMISSION/RECEPTION DEVICE USING SAME - Provided are a transmission/reception antenna and a transmission/reception device using the same wherein the transmission/reception antenna comprises an excitation loop antenna ( | 05-17-2012 |
20120208474 | TRANSMISSION/RECEPTION ANTENNA AND TRANSMISSION/RECEPTION DEVICE USING SAME - Provided are a transmission/reception antenna and a transmission/reception device using the same wherein the transmission/reception antenna comprises a dielectric base board ( | 08-16-2012 |
20150054351 | POWER TRANSMITTING DEVICE, ELECTRONIC EQUIPMENT AND WIRELESS POWER TRANSMISSION SYSTEM - Reduction in the power transmission efficiency due to imprecise positioning between a primary power transmission coil and a secondary power reception coil is avoided. For transmitting electric power in a wireless manner to an electronic device including a secondary power reception coil and configured to receive electric power via the secondary power reception coil, a power transmission device includes a primary power transmission coil and a power transmission circuit unit for supplying electric power to the primary power transmission coil, and a transmission circuit unit is formed by the primary power transmission coil and the secondary power reception coil. A first impedance of an input end of the transmission circuit unit is matched with a second impedance of an output end of the transmission circuit unit by using a coupling coefficient between the primary power transmission coil and the secondary power reception coil. | 02-26-2015 |
20150236517 | CONTACTLESS ELECTRIC POWER FEEDING SYSTEM - Provided is a contactless electric power feeding system that allows a plurality of devices to be recharged at the same time. A feeding device includes a primary feeding coil and each receiving device includes a secondary receiving coil. Each coil forms a resonance circuit jointly with a capacitor, and the two resonance circuits are electro-magnetically coupled with each other to from a transmission circuit unit. A first impedance of an input end of the transmission circuit unit is matched with a second impedance of an output end of the transmission circuit unit by using a coupling efficient between the primary feeding coil and the secondary receiving coil, and the output impedance of a power supply unit for supplying electric power to the primary feeding coil is smaller than the first impedance. | 08-20-2015 |
Patent application number | Description | Published |
20100264979 | MIXER CIRCUIT - In a mixer circuit, addition of analog signals by capacitive coupling is used and square-law characteristics of the drain current of a MOS transistor operating in a saturated region are used. With this configuration, the voltage and power of the mixer circuit can be reduced. | 10-21-2010 |
20110037510 | MIXER CIRCUIT - In a mixer circuit, addition of analog signals by capacitive coupling is used and square-law characteristics of the drain current of a MOS transistor operating in a saturated region are used. With this configuration, the voltage and power of the mixer circuit can be reduced. | 02-17-2011 |
20120063520 | SEMICONDUCTOR INTEGRATED CIRCUIT, RADIO COMMUNICATION DEVICE AND TIME TO DIGITAL CONVERTER - According to one embodiment, a semiconductor integrated device includes a digitally controlled oscillator, a counter, a time to digital converter, an adder, and a control signal generator. The time to digital converter includes a frequency-divider, a plurality of impedance elements, and a phase difference detector. The frequency-divider is configured to frequency-divide the oscillation signal to generate a plurality of frequency-divided signals. The plurality of impedance elements is configured to voltage-divide the frequency-divided signals to generate a plurality of delay signals of the oscillation signal. The phase difference detector is configured to output the third digital signal corresponding to the phase difference between the reference signal and the oscillation signal by comparing the reference signal with each of the delay signals. | 03-15-2012 |
20120064844 | SEMICONDUCTOR INTEGRATED CIRCUIT AND RADIO COMMUNICATION DEVICE - According to one embodiment, a semiconductor integrated circuit includes a phase shifter, a plurality of phase matching detecting circuits, a output module. The phase shifter is configured to delay an input oscillation signal to generate a plurality of delay signals having phases different from each other. The plurality of phase matching detecting circuits is configured to store a second program for downloading a first program from an outside to the first area. The output module is configured to generate an output oscillation signal based on at least one of the delay signals having the phase difference determined to be within the predetermined range. | 03-15-2012 |
20120238221 | RADIO COMMUNICATION DEVICE, TRANSMISSION CIRCUIT AND BUFFER CIRCUIT - According to one embodiment, a buffer circuit has a capacitor comprising a first terminal and a second terminal, an input signal being inputted to the first terminal, a first inverting amplifier circuit configured to invert and amplify a signal of the second terminal of the capacitor, a second inverting amplifier circuit configure to invert and amplify an output signal of the first inverting amplifier circuit, and a MOS (Metal Oxide Semiconductor) transistor comprising a third terminal, a fourth terminal and a gate, the third terminal being connected to the second terminal of the capacitor, the fourth terminal being connected to a connection node of the first and the second inverting amplifier circuits, an inversion signal of the input signal being inputted to the gate. | 09-20-2012 |
20120242314 | DC-DC CONVERTER AND DIGITAL PULSE WIDTH MODULATOR - A DC-DC converter has a switching element, a lowpass filter, an oscillator, an AD converter, an error signal generator, a counter, a comparator, a selector configured to select one of the plurality of clock signals in accordance with a value of a lower side bit of the error signal in sync with a timing when the comparator detects coincidence, and a switching controller configured to control ON/OFF of the switching element in accordance with the clock signal selected by the selector. The selector selects one among the plurality of clock signals and a new clock signal generated by combining two or more clock signals comprising neighboring phases among the plurality of clock signals. | 09-27-2012 |
20120242414 | SEMICONDUCTOR INTEGRATED CIRCUIT AND RECEIVING APPARATUS - According to one embodiment, a semiconductor integrated circuit has a transconductance circuit, a first load circuit, and a second load circuit. The transconductance circuit has a first current generator configured to generate a first current depending on an input voltage, and a second current generator configured to generate a second current depending on the input voltage. The first load circuit has a first load configured to output a first output voltage depending on the first current from a first output terminal. The second load circuit has a second load configured to output a second output voltage depending on the second current from a second output terminal. At least one of the transconductance circuit, the first load circuit and the second load circuit comprises an impedance adjusting module configured to adjust impedance. | 09-27-2012 |
20130242201 | TRANSMISSION SYSTEM AND TRANSMITTER - According to one embodiment, a transmission system includes a transmitter, and a receiver. The transmitter includes one or a plurality of light sources, a modulator, a first driver, a display, and a second driver. The one or a plurality of light sources is configured to emit a visible light whose light amount corresponds to a first drive signal. The modulator is configured to, according to transmission data to be transmitted from the transmitter to the receiver, modulate a first luminance signal indicative of an amount of the light the light source is configured to emit, to generate a second luminance signal. The first driver is configured to generate the first drive signal based on the second luminance signal. A mean of the second luminance signal during one frame in the input video signal is substantially equal to a value of the first luminance signal in the frame. | 09-19-2013 |
20130251375 | RECEIVER, TRANSMITTER AND COMMUNICATION SYSTEM - According to one embodiment, a receiver includes an image sensor, a synchronization controller, and a data generator. The image sensor detects a visible ray having a lattice-shaped emission pattern. The synchronization controller determines whether it is necessary to generate data based on a first synchronized visible ray located at a first lattice corner of the emission pattern and a second synchronized visible ray located at a second lattice corner. The second lattice corner is an opposite corner to the first lattice corner. The data generator generates the data corresponding to a data visible ray located at a lattice point other than the first lattice corner and the second lattice corner when the synchronization controller determines that it is necessary to generate the data. | 09-26-2013 |
20130252559 | DA CONVERTER AND WIRELESS COMMUNICATION APPARATUS - In general, according to one embodiment, a DA converter configured to convert a digital signal comprising n (n>1) bits to an analog current to output the analog current from an output terminal, includes n voltage-current converters. Each of them corresponds to each bit of the digital signal and is configured to generate a current depending on the corresponding bit. A k-th (k is an integer of 0 to n−1) voltage-current converter includes a first transistor whose threshold voltage is adjustable. The first transistor includes a semiconductor substrate, a first diffusion region, a second diffusion region, an insulating film, a charge accumulating film, and a gate. | 09-26-2013 |
20130271631 | LIGHT RECEIVER, LIGHT RECEPTION METHOD AND TRANSMISSION SYSTEM - According to one embodiment, a light receiver includes a light reception module, a multi-exposure area selector, a multi-exposure controller, and a readout module. The light reception module includes N lines, each of the N lines having a plurality of light receiving elements. The multi-exposure area selector is configured to select one or a plurality of single-exposure lines and one or a plurality of multi-exposure lines. The multi-exposure controller is configured to, per the unit time, perform an exposure on the single-exposure lines one time for a first exposure time; and a first exposure and a second exposure on the multi-exposure lines. The readout module is configured to read exposure amounts of the lines line by line. The multi-exposure controller is configured to start the second exposure on the multi-exposure lines before reading of the exposure amounts of all the single-exposure lines is completed. | 10-17-2013 |
20130272717 | TRANSMISSION SYSTEM, TRANSMITTER AND RECEIVER - According to one embodiment, a transmission system includes a transmitter and a receiver. The transmitter includes a modulator configured to modulate transmission data at a chip rate to generate a modulation signal, and one or a plurality of light sources configured to emit visible light according to the modulation signal. The receiver includes a light receiver having one or more lines of light receiving elements to receive light in a first range including the visible light; and a demodulator configured to demodulate image data generated according to the light received by the light receiver to generate reception data corresponding to the transmission data. A following equation is satisfied ff10-17-2013 | |
20140008518 | IMAGE SENSOR CIRCUIT - The controlling circuit of the image censor circuit controls the row decoder to address the light receiving cell with the address signal to turn on the first MOS transistor and turns on the switch circuit with a switch controlling signal, and then controls the row decoder to turn off the first MOS transistor and then turns off the switch circuit with the switch controlling signal. | 01-09-2014 |
20140070074 | SEMICONDUCTOR INTEGRATED CIRCUIT AND IMAGE SENSOR - According to one embodiment, a semiconductor integrated circuit includes: a CDS (Correlated Double Sampling) circuit; and an adjustment voltage generator. The CDS circuit has a first capacitor and a second capacitor. The first capacitor has a first electrode and a second electrode. The second capacitor has a third electrode and a fourth electrode. The CDS circuit is configured to hold a voltage corresponding to light intensity as a signal voltage. The adjustment voltage generator is configured to supply an adjustment voltage to the CDS circuit. A first signal voltage is supplied to the first electrode, and a second signal voltage is supplied to the third electrode. The second electrode and the fourth electrode are commonly connected and supplied with the adjustment voltage from the adjustment voltage generator. | 03-13-2014 |
20140070975 | SEMICONDUCTOR INTEGRATED CIRCUIT AND IMAGE SENSOR - According to one embodiment, a semiconductor integrated circuit is configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal. The semiconductor integrated circuit includes m (m is an integer greater than or equal to 2) first capacitors and second capacitors. Each of the m capacitors has a first electrode and a second electrode, and the first electrodes are connected to each other. Each of the m second capacitors has a third electrode and a fourth electrode, and the third electrodes are connected to each other. The semiconductor integrated circuits further includes: a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; and a logic circuit configured to generate the digital signal based on a comparison result of the comparator. | 03-13-2014 |
20140104930 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state. | 04-17-2014 |
20140287700 | RADIO COMMUNICATION DEVICE, TRANSMISSION CIRCUIT AND BUFFER CIRCUIT - According to one embodiment, a buffer circuit has a capacitor comprising a first terminal and a second terminal, an input signal being inputted to the first terminal, a first inverting amplifier circuit configured to invert and amplify a signal of the second terminal of the capacitor, a second inverting amplifier circuit configure to invert and amplify an output signal of the first inverting amplifier circuit, and a MOS (Metal Oxide Semiconductor) transistor comprising a third terminal, a fourth terminal and a gate, the third terminal being connected to the second terminal of the capacitor, the fourth terminal being connected to a connection node of the first and the second inverting amplifier circuits, an inversion signal of the input signal being inputted to the gate. | 09-25-2014 |
20150068314 | MEMS DEVICE - According to one embodiment, a MEMS device is disclosed. The device includes a substrate, a first and second MEMS elements on the substrate. Each of the first and second MEMS elements includes a fixed electrode on the substrate, a movable electrode above the fixed electrode, a first insulating film, the first insulating film and the substrate defining a cavity in which the fixed and movable electrodes are contained, and a first anchor on a surface of the first insulating film inside the cavity and configured to connect the movable electrode to the first insulating film. The cavity of the first MEMS element is closed. The cavity of the second MEMS element is opened by a through hole. | 03-12-2015 |
20150233972 | CAPACITANCE DETECTION DEVICE - According to one embodiment, a capacitance detection device includes a switched capacitor amplifying circuit including a variable capacitor and a reference capacitor, and a voltage applying circuit configured to apply, to the switched capacitor amplifying circuit, a reference voltage having a temperature characteristic for compensating fluctuation in an output voltage of the switched capacitor amplifying circuit due to a temperature characteristic of capacitance of the variable capacitor. | 08-20-2015 |
Patent application number | Description | Published |
20120140147 | DISPLAY PANEL, DISPLAY SYSTEM, PORTABLE TERMINAL AND ELECTRONIC DEVICE - To provide a display panel that can achieve a transparent state having high panel transmittance and that can carry out a display in which a figure looks as if it has popped up in the air, a display panel disclosed includes a PDLC panel ( | 06-07-2012 |
20120320443 | BUILDING MATERIAL WITH DISPLAY DEVICE, AND DISPLAY DEVICE - A building material in which an image can be displayed on a transparent plate such as a windowpane is realized using a configuration that is simple and low-cost. A window member ( | 12-20-2012 |
20130044280 | DISPLAY DEVICE - A display device capable of emitting sufficient fluorescence is provided without an increase in the thickness of the liquid crystal layer. The device includes: a fluorescent emission layer ( | 02-21-2013 |
20130194524 | DISPLAY PANEL AND DISPLAY DEVICE PROVIDED WITH SAME - A liquid crystal panel includes a liquid crystal layer that can switch to a light transmitting state and a light scattering state, and lines provided on a portion of the liquid crystal layer on the side opposite to the observation side. The lines are provided with a reflecting portion by which at least a portion of light that entered from the observation side is reflected toward the observation side. | 08-01-2013 |
20130208201 | DISPLAY DEVICE - A display device ( | 08-15-2013 |
20130265629 | DISPLAY DEVICE - A display device ( | 10-10-2013 |
20130286334 | DISPLAY DEVICE - A display device ( | 10-31-2013 |
20140092347 | LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE - A variable reflectance mirror ( | 04-03-2014 |
20140124158 | COOLING EQUIPMENT, TEMPERATURE CONTROL SYSTEM, AIR CONDITIONING SYSTEM, AND HOT WATER SUPPLY SYSTEM FOR THE SAME - The present invention aims to provide cooling equipment which can reduce power consumption. Cooling equipment | 05-08-2014 |
20140240652 | SEE-THROUGH DISPLAY DEVICE, AND ELECTRICAL DEVICE AND FURNITURE PIECE EACH OF WHICH IS PROVIDED WITH SEE-THROUGH DISPLAY DEVICE - A see-through display device ( | 08-28-2014 |
20150114592 | LATENT HEAT STORAGE MEMBER AND BUILDING MATERIAL PROVIDED WITH SAME, MICROCAPSULES AND THERMAL STORAGE MATERIAL USING MICROCAPSULES - The present invention is to provide a latent heat storage member which is able to more reliably contribute to a daily peak shift of energy consumption, and a building material provided with the latent heat storage member. A latent heat storage member | 04-30-2015 |
20150153087 | STORAGE CONTAINER - An object is to provide a storage container including latent heat storage materials that provide a high cold insulation effect. A storage container | 06-04-2015 |
Patent application number | Description | Published |
20080249717 | Method and apparatus for chromatographic data processing - A chromatographic analyzer is provided for facilitating curve fitting by means of the linear least-square method for a chromatogram that contains a plurality of overlapping peaks. The present invention is characterized by a chromatographic data processor for executing data processing of a chromatogram obtained by separating a sample to be measured using a column and detecting the separated sample, wherein fitting processing is executed to each peak in an arbitrary time region having the plurality of peaks of the chromatogram starting from the front side of the time region or from the back side of the time region, and the processed peaks are subtracted from the chromatogram in the time region so that the plurality of peaks in the chromatogram can be separated from one another. Thus, the plurality of overlapping peaks, particularly three or more overlapping peaks in the chromatogram can be easily separated from one another only by defining some setting conditions. | 10-09-2008 |
20100057379 | METHOD AND APPARATUS FOR CHROMATOGRAPHIC DATA PROCESSING - A chromatographic analyzer is provided for facilitating curve fitting by means of the linear least-square method for a chromatogram that contains a plurality of overlapping peaks. The present invention is characterized by a chromatographic data processor for executing data processing of a chromatogram obtained by separating a sample to be measured using a column and detecting the separated sample, wherein fitting processing is executed to each peak in an arbitrary time region having the plurality of peaks of the chromatogram starting from the front side of the time region or from the back side of the time region, and the processed peaks are subtracted from the chromatogram in the time region so that the plurality of peaks in the chromatogram can be separated from one another. Thus, the plurality of overlapping peaks, particularly three or more overlapping peaks in the chromatogram can be easily separated from one another only by defining some setting conditions. | 03-04-2010 |
20110098940 | METHOD AND APPARATUS FOR CHROMATOGRAPHIC DATA PROCESSING - A chromatographic analyzer is provided for facilitating curve fitting by means of the linear least-square method for a chromatogram that contains a plurality of overlapping peaks. The present invention is characterized by a chromatographic data processor for executing data processing of a chromatogram obtained by separating a sample to be measured using a column and detecting the separated sample, wherein fitting processing is executed to each peak in an arbitrary time region having the plurality of peaks of the chromatogram starting from the front side of the time region or from the back side of the time region, and the processed peaks are subtracted from the chromatogram in the time region so that the plurality of peaks in the chromatogram can be separated from one another. Thus, the plurality of overlapping peaks, particularly three or more overlapping peaks in the chromatogram can be easily separated from one another only by defining some setting conditions. | 04-28-2011 |
20120055581 | LIQUID DELIVERY DEVIDE AND LIQUID CHROMATOGRAPHY DEVICE - In a liquid delivery device, when an inlet-side check valve and an outlet-side check valve of a first cylinder are both closed, and compression of an eluent inside the first cylinder is started by means of a first plunger inside the first cylinder, a control unit doubles the rotational speed of a step motor, and measures the amount of change in the pressure inside the first cylinder which changes for a prescribed time by means of a first cylinder internal pressure detector. The time elapsed until the pressure inside the first cylinder is the same as the pressure inside a discharge-side flow passage is predicted using the rate of change over time of the pressure of the eluent. When the predicted elapsed time has elapsed, the rotational speed of the step motor is returned to the original speed, and the compression of the eluent inside the first cylinder is completed. | 03-08-2012 |
20120128533 | LIQUID SUPPLY DEVICE USING CHECK VALVE AND REACTIVE LIQUID CHROMATOGRAPHY SYSTEM - It is possible to correctly determine whether a change in the pressure or flow rate is caused by normal opening and closing operations of a check valve and to monitor in real time whether an operation of a check valve is normal or abnormal in a liquid supply device. Light is introduced in the check valve and a change in the quantity of light transmitted through or reflected by the check valve, caused by the opening and closing of the valve is detected, so that the opening and closing operations of the check valve can be directly detected. The check valve is arranged in a pipe in the liquid supply device, and a change in the pressure in the pipe is monitored on the basis of a signal from a pressure sensor and a signal which represents the opening and closing of the check valve. | 05-24-2012 |
Patent application number | Description | Published |
20110198641 | Semiconductor light-emitting element - A semiconductor light-emitting element includes a semiconductor laminated structure including a light-emitting layer sandwiched between first and second conductivity type layers for extracting an emitted light from the light-emitting layer on a side of the second conductivity type layer, a transparent electrode in ohmic contact with the second conductivity type layer, an insulation layer formed on the transparent electrode, an upper electrode for wire bonding formed on the insulation layer, a lower electrode that penetrates the insulation layer, is in ohmic contact with the transparent electrode and the electrode for wire bonding, and has an area smaller than that of the upper electrode in top view, and a reflective portion for reflecting at least a portion of light transmitted through a region of the transparent electrode not in contact with the lower electrode. | 08-18-2011 |
20110233588 | Semiconductor light-emitting device - A first intermediate electrode | 09-29-2011 |
20120138984 | Semiconductor light emitting element - A semiconductor light emitting element includes a semiconductor multilayer structure including a first conductive type layer, a second conductive type layer, and a light emitting layer sandwiched between the first conductive type layer and the second conductive type layer, and a reflecting layer formed on the second conductive type layer for reflecting the light emitted from the light emitting layer. The light is extracted in a direction from the light emitting layer toward the first conductive type layer. The first conductive type layer includes a concavo-convex region on a surface thereof not opposite to the light emitting layer, for changing a path of light, and at least a part of the reflecting layer is formed extending to right above an edge of the concavo-convex region. | 06-07-2012 |
20120146075 | Semiconductor light emitting element - A semiconductor light emitting element includes a semiconductor multilayer structure including a first conductive type layer, a second conductive type layer and a light emitting layer sandwiched between the first conductive type layer and the second conductive type layer, a first transparent electrode formed on the second conductive type layer, a reflecting layer formed on the first transparent electrode, and including a smaller area than the first transparent electrode, a second transparent electrode formed on the first transparent electrode so as to cover the reflecting layer, and a pad electrode formed on the second transparent electrode and in a region above the reflecting layer. | 06-14-2012 |
20120241720 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A Group III nitride semiconductor light-emitting device, includes a groove having a depth extending from the top surface of a p-type layer to an n-type layer is provided in a region overlapping (in plan view) with the wiring portion of an n-electrode or the wiring portion of a p-electrode. An insulating film is provided so as to continuously cover the side surfaces and bottom surface of the groove, the p-type layer, and an ITO electrode. The insulating film incorporates therein reflective films in regions directly below the n-electrode and the p-electrode (on the side of a sapphire substrate). The reflective films in regions directly below the wiring portion of the n-electrode and the wiring portion of the p-electrode are located at a level lower than that of a light-emitting layer. The n-electrode and the p-electrode are covered with an additional insulating film. | 09-27-2012 |
20120244653 | METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - A reflective film including Ag of an Ag alloy is patterned in a uniform thickness without decreasing reflectivity. The reflective film is formed on the entire surface of a first insulating film by sputtering, vacuum deposition or the like, and a barrier metal film having a given pattern is formed on the reflective film by a lift-off method. The reflective film is wet etched using a silver etching liquid. The barrier metal film is not wet etched by the silver etching liquid, and therefore functions as a mask, and the reflective film in a region on which the barrier metal film has been formed remains not etched. As a result, the reflective film having a desired patter can uniformly be formed on the first insulating film. | 09-27-2012 |
20130203194 | METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - Sample A is produced by sequentially forming a first insulating film of SiO | 08-08-2013 |
20140070227 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor light emitting element comprises steps of forming a semiconductor layer composed of a Group III nitride based compound semiconductor on a principal surface of a substrate; forming a transparent conductive metal oxide film on the semiconductor layer; forming an electrode above the transparent conductive metal oxide film; forming a mask layer for covering a part of the transparent conductive metal oxide film; and heat treating the transparent conductive metal oxide film having the mask layer formed thereon in an oxygen-containing atmosphere; wherein, in the heat treatment step, an oxygen concentration of a remaining part of the transparent conductive metal oxide film which is not covered by the mask layer is made higher than an oxygen concentration of a part of the transparent conductive metal oxide film which is covered by the mask layer. | 03-13-2014 |
20140183586 | LIGHT EMITTING ELEMENT - A light emitting element includes a semiconductor laminate structure including a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type, a part of the second semiconductor layer and the light emitting layer being removed to expose a part of the first semiconductor layer, a first reflecting layer located on the semiconductor laminate structure and including an opening, the opening being formed in the exposed part of the first semiconductor layer, a transparent wiring electrode for carrier injection into the first semiconductor layer or the second semiconductor layer through the opening, and a second reflecting layer formed on the transparent wiring electrode and covering a part of the opening so as to reflect light emitted from the light emitting layer and passing through the opening back to the first semiconductor layer. | 07-03-2014 |
20150083997 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A face-up-type Group III nitride semiconductor light-emitting device includes a growth substrate, an n-type layer, a light-emitting layer, a p-type layer, an n-electrode including a bonding portion and a wiring portion, a p-electrode including a bonding portion and a wiring portion, and a first insulating film. The n-type layer, the light-emitting layer, and the p-type layer are sequentially stacked on the growth substrate, and the n-electrode and the p-electrode are formed on the first insulating film. A groove having a depth extending from a top surface of the p-type layer to the n-type layer is formed in at least one region selected from a region directly below the wiring portion of the n-electrode and a region directly below the wiring portion of the p-electrode. The wiring portion, which is formed in the groove, is located at a level lower than that of the light-emitting layer. | 03-26-2015 |
Patent application number | Description | Published |
20120135148 | SUBSTRATE TREATMENT SYSTEM, SUBSTRATE TREATMENT METHOD, AND NON-TRANSITORY COMPUTER STORAGE MEDIUM - A substrate treatment system includes a plurality of treatment apparatuses, a position adjustment apparatus adjusting a center position of the substrate, a substrate transfer apparatus transferring the substrate to the treatment apparatuses and the position adjustment apparatus, and a control unit controlling operations of the apparatuses. The substrate transfer apparatus includes an arm part curved along a peripheral edge portion of the substrate with a radius of curvature larger than a radius of the substrate, and a holding part projecting inward from the arm part and holding a rear surface of the substrate. The position adjustment apparatus includes a mounting table which holds a central portion of the rear surface of the substrate and is rotatable and horizontally movable. The control unit controls the mounting table such that the center position of the substrate held on the mounting table is aligned with a center position of the arm part. | 05-31-2012 |
20130000684 | CLEANING METHOD AND CLEANING APPARATUS - A cleaning method of cleaning a joint surface of a processing target substrate separated from a superposed substrate, while the processing target substrate is placed inside an annular frame and held by a tape bonded to a surface of the frame and a non-joint surface of the processing target substrate, the cleaning method including: a placement step of placing a cleaning jig to face the processing target substrate such that a supply surface of the cleaning jig for supplying a solvent for the adhesive onto the joint surface of the processing target substrate covers the joint surface and a distance between the supply surface and the joint surface is a predetermined distance; and a cleaning step of then supplying the solvent between the supply surface and the joint surface and diffusing the supplied solvent over the joint surface by a surface tension. | 01-03-2013 |
20130062013 | JOINT APPARATUS, JOINT SYSTEM, AND JOINT METHOD - A joint apparatus that joins a processing target substrate and a supporting substrate together, includes: a processing container that is capable of hermetically closing an inside thereof; a joint unit that joins the processing target substrate and the supporting substrate together by pressing the processing target substrate and the supporting substrate via an adhesive; and a superposed substrate temperature regulation unit that temperature-regulates a superposed substrate joined in the joint unit, wherein the joint unit and the superposed substrate temperature regulation unit are arranged in the processing container, A delivery unit for delivering the processing target substrate, the supporting substrate, or the superposed substrate to/from an outside of the processing container is provided in the processing container, and the superposed substrate temperature regulation unit is provided in the delivery unit. | 03-14-2013 |
20130071996 | JOINT METHOD, JOINT APPARATUS AND JOINT SYSTEM - When joining a processing target substrate and a supporting substrate together by suction-holding the processing substrate and the supporting substrate respectively on a first holding unit and a second holding unit arranged to face each other and pressing the second holding unit toward the first holding unit while heating the substrates by heating mechanisms of the holding units, the present invention preheats at least the processing target substrate before suction-holding the processing target substrate on the first holding unit to suppress generation of particles when joining the processing target substrate and the supporting substrate together so as to properly perform the joining of the processing target substrate and the supporting substrate. | 03-21-2013 |
20140251546 | PEELING DEVICE, PEELING SYSTEM AND PEELING METHOD - A peeling device according to the present disclosure includes a holding unit, a plurality of suction moving units, a state detection unit and a control unit. The holding unit is configured to hold a first substrate of a superposed substrate having the first substrate and a second substrate joined. The suction moving units are configured to suction-hold the second substrate of the superposed substrate and move the second substrate in a direction away from a surface of the first substrate. The state detection unit is configured to detect a peeled-off state of the second substrate from the first substrate. The control unit is configured to control operation timings of the suction moving units so that the second substrate is peeled off from the first substrate gradually from one end of the second substrate toward the other end thereof, based on the peeled-off state detected by the state detection unit. | 09-11-2014 |
20140284000 | SEPARATION APPARATUS, SEPARATION SYSTEM, SEPARATION METHOD AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM - A separation apparatus for separating a superposed substrate into a processing target substrate and a supporting substrate, includes: one holding part holding the processing target substrate via a tape; another holding part holding the supporting substrate; and a moving mechanism moving the another holding part in a vertical direction while holding an outer peripheral portion thereof to continuously separate the supporting substrate held by the another holding part from the processing target substrate held by the one holding part starting from an outer peripheral portion toward a central portion of the supporting substrate, wherein the moving mechanism includes: a first moving part holding the another holding part and moving only the outer peripheral portion of the another holding part in the vertical direction; and a second moving part moving the first moving part and the another holding part in the vertical direction. | 09-25-2014 |
20140335633 | SEPARATION METHOD, COMPUTER STORAGE MEDIUM, AND SEPARATION SYSTEM - A superposed wafer is separated to a processing target wafer and a supporting wafer while being heated. Then, an adhesive on a joint surface of the processing target wafer is removed by supplying an organic solvent onto the joint surface of the processing target wafer. Then, an oxide film formed on the predetermined pattern on the joint surface of the processing target wafer is removed by supplying acetic acid to the joint surface of the processing target wafer. Then, the joint surface of the processing target wafer is inspected. Then, based on an inspection result, the adhesive on the joint surface of the processing target wafer is removed and the oxide film formed on the predetermined pattern on the joint surface of the processing target wafer is removed. | 11-13-2014 |
20150251398 | BONDING SYSTEM AND BONDING METHOD - Provided is a bonding system, which includes: a processing station in which specified processes are performed on a first substrate and a second substrate; and a carry-in/carry-out station in which the first substrate, the second substrate or a laminated substrate obtained by bonding the first substrate and the second substrate is carried into and out of the processing station. The processing station includes: a first processing apparatus configured to coat the first substrate with the bonding agent using a bonding agent injecting part; a second processing apparatus provided with a bevel cleaning unit for cleaning a bevel portion of the first substrate coated with the bonding agent; and a bonding apparatus configured to bond the first substrate and the second substrate through the bonding agent and a release agent. The first processing apparatus or the second processing apparatus further includes a release agent injection part for injecting the release agent. | 09-10-2015 |
Patent application number | Description | Published |
20080218283 | Triangular wave generating circuit, and charging and discharging control circuit - A triangular wave generating circuit capable of reducing a time lag between the time of input of a discharging start signal and the time of start of actual discharging is provided. A charging and discharging circuit of the triangular wave oscillation circuit includes: an inverter circuit; a discharging reference potential generating circuit; a first NMOS transistor having a drain connected with a connection point between a first current source circuit and the capacitor, and a gate connected with the discharging reference potential generated by the discharging reference potential generating circuit; a second NMOS transistor having a gate inputted with the switching signal through the inverter circuit, a drain connected with the gate of the first NMOS transistor, and a source connected with a source of the first NMOS transistor; and a third NMOS transistor having a gate inputted with the switching signal, a drain connected with a connection point between the source of the first NMOS transistor and the source of the second NMOS transistor, and a source grounded. | 09-11-2008 |
20090167410 | POWER SUPPLY SWITCHING CIRCUIT - Provided is a power supply switching circuit capable of efficiently supplying a desired voltage among a plurality of voltages to a load. In the case of a P-type semiconductor substrate, N-type MOS transistors are provided between a load and an AC adapter and between the load and a battery, and hence no parasitic diode exists between the load and the AC adapter or the battery, resulting in no current path due to the parasitic diode. Thus, when the AC adapter and the battery are connected to the power supply switching circuit, the N-type MOS transistor is turned off, whereby the current path between the battery and the load is cut off completely and the N-type MOS transistor is turned on. Accordingly, the battery cannot supply a voltage to the load while only the AC adapter can supply a voltage to the load. | 07-02-2009 |
20110181262 | SWITCHING REGULATOR - Provided is a switching regulator capable of performing stable start-up with a soft-start operation without causing excessive extension of a soft-start time period. In a start-up period, a voltage approximating a feedback voltage (FB) is provided as an initial value of a soft-start reference voltage. The feedback voltage (FB) and the soft-start reference voltage become substantially equal to each other at a moment when the start-up is completed, to thereby realize a smooth transition of an operating state from the start-up to normal control. | 07-28-2011 |
20120194154 | SWITCHING REGULATOR CONTROL CIRCUIT AND SWITCHING REGULATOR - Provided is a switching regulator including an overload protection circuit, which has high accuracy even without requiring adjusting means in a test step. The switching regulator includes: a first triangle wave generation circuit for generating a first triangle wave which controls Duty of a PWM signal; and a second triangle wave generation circuit for generating a second triangle wave for overload detection, which has a crest value smaller than that of the first triangle wave. A ratio between the crest value of the first triangle wave and the crest value of the second triangle wave is set based on respective capacitances or constant currents thereof. | 08-02-2012 |
20120313601 | SWITCHING REGULATOR - In order to provide a switching regulator having high efficiency even under light load, the switching regulator is configured so that ON/OFF of a switching element is controlled by an output signal of an oscillation circuit having an oscillation frequency controlled by an output signal from an error amplifier. Thereby, the oscillation frequency can be suppressed under light load, thus reducing a switching loss. | 12-13-2012 |
20130207633 | SWITCHING REGULATOR - Provided is a switching regulator including a circuit for detecting a short-circuit state easily and reliably, without the need of an adjustment step such as trimming. In accordance with a drive signal of a power switching element of the switching regulator, a discharge circuit is controlled. When the power switching element is short-circuited and becomes the ON state all the time, the discharge circuit stops its operation, and a capacitor is continuously charged. A voltage detection circuit detects that a charge voltage of the capacitor has reached a predetermined potential, to thereby detect the short-circuit state. | 08-15-2013 |
20140247523 | SWITCHING REGULATOR AND ELECTRONIC DEVICE - There is provided a switching regulator including an overcurrent protection circuit which is able to automatically return from an overcurrent state. The switching regulator includes an error amplification circuit which amplifies a difference between a feedback voltage and a reference voltage based on an output voltage and outputs the amplified difference; a PWM comparator which compares an output of the error amplification circuit with an output of a triangular wave oscillation circuit, and controls an output transistor; an overcurrent detection circuit which monitors a load current flowing through a load connected to an output terminal, detects that the load current is an overcurrent, and outputs an overcurrent detection signal causing a switching operation to stop; and a negative feedback control circuit which receives the overcurrent detection signal, and controls the load current to a predetermined current value. | 09-04-2014 |
20150180335 | SWITCHING REGULATOR AND ELECTRONIC APPARATUS - A switching regulator is provided which can prevent overshooting in an output voltage even when a source voltage is returned to a normal voltage from a voltage lower than a desired output voltage of the switching regulator. The switching regulator includes a 100% duty detector circuit that detects that a PWM comparator is in a 100%-duty state and a discharge accelerator circuit that detects that the output of an error amplifier discharges the voltage of a phase compensating capacitor and that accelerates the discharge, and activates the discharge accelerator circuit when the 100% duty detector circuit detects the 100%-duty state. | 06-25-2015 |
20150222180 | SWITCHING REGULATOR CONTROL CIRCUIT AND SWITCHING REGULATOR - Provided is a switching regulator configured to achieve a 100% Duty state and reduce an occurrence of an overshoot. The switching regulator has a configuration in which a clamp circuit configured to dynamically generate a clamp level clamps an output voltage of an error amplifier in accordance with a peak value of a triangular wave signal. | 08-06-2015 |
Patent application number | Description | Published |
20080279259 | Radio Communication Apparatus, Base Station and System - Radio communication apparatus for receiving OFDM signal from base station and transmitting FH signal to base station, using sub-channels, base station comparing hopping pattern information items indicating hopping patterns from radio communication apparatuses including radio communication apparatus, and generating collision information when hopping patterns include colliding hopping patterns, includes estimation unit configured to estimate channel response values of sub-channels based on OFDM signal, selector which selects, from sub-channels, several sub-channels which have higher channel response values than a value, each of channel response values being expressed by power level, signal-to-noise power ratio, or signal-to-interference ratio, determination unit configured to determine hopping pattern from selected sub-channels, transmitter which transmits, to base station, hopping pattern information item indicating determined hopping pattern, receiver which receives collision information from base station, and correction unit configured to correct hopping pattern based on collision information. | 11-13-2008 |
20110069781 | WIRELESS COMMUNICATION APPARATUS, WIRELESS COMMUNICATION SYSTEM, AND TRANSMISSION METHOD - A wireless communication apparatus (a) generates a transmission symbol; (b) assigns, to the transmission symbol, a given number of units each formed of a symbol and a subcarrier in a frame which is formed of M (M is a positive integer) symbols and N (N is a positive integer) subcarriers and includes M×N units, and the given number being not more than M×N, to obtain the given number of identical transmission symbols; (c) multiplies the identical transmission symbols by a code sequence including a plurality of different elements; and (d) transmits the identical transmission symbols multiplied by the code sequence. | 03-24-2011 |
20130163402 | WIRELESS COMMUNICATION APPARATUS, WIRELESS COMMUNICATION SYSTEM, AND TRANSMISSION METHOD - A wireless communication apparatus (a) generates a transmission symbol; (b) assigns, to the transmission symbol, a given number of units each formed of a symbol and a subcarrier in a frame which is formed of M (M is a positive integer) symbols and N (N is a positive integer) subcarriers and includes M×N units, and the given number being not more than M×N, to obtain the given number of identical transmission symbols; (c) multiplies the identical transmission symbols by a code sequence including a plurality of different elements; and (d) transmits the identical transmission symbols multiplied by the code sequence. | 06-27-2013 |