# David Raymond Lutz, Austin US

## David Raymond Lutz, Austin, TX US

Patent application number | Description | Published |
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20110004743 | Pipe scheduling for pipelines based on destination register number - A data processing apparatus | 01-06-2011 |

20110072066 | Apparatus and method for performing fused multiply add floating point operation - A fused multiply add floating point unit | 03-24-2011 |

20110106868 | Floating point multiplier with partial product shifting circuitry for result alignment - A floating point multiplier includes a data path in which a plurality of partial products are calculated and then reduced to a first partial product and a second partial product. Shift amount determining circuitry | 05-05-2011 |

20110276614 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A RECIPROCAL OPERATION ON AN INPUT VALUE TO PRODUCE A RESULT VALUE - A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step performing the computation: X | 11-10-2011 |

20120215823 | Apparatus and method for performing floating point addition - An apparatus and method are provided for performing an addition operation on operands A and B in order to produce a result R, the operands A and B and the result R being floating point values each having a significand and an exponent. The apparatus comprises prediction circuitry for generating a shift indication based on a prediction of the number of leading zeros that would be present in an output produced by subjecting the operands A and B to an unlike signed addition. Further, result pre-normalization circuitry performs a shift operation on the significands of both operand A and operand B prior to addition of the significands, this serving to discard a number of most significant bits of the significands of both operands as determined by the shift indication in order to produce modified significands for operands A and B. Operand analysis circuitry detects, with reference to the exponents of operands A and B, the presence of a leading bit cancellation condition, and addition circuitry is configured, in the presence of the leading bit cancellation condition, to perform an addition of the modified significands for operands A and B, in order to produce the significand of the result R. Such an approach provides a particularly simple and efficient apparatus for performing addition operations. | 08-23-2012 |

20130151576 | APPARATUS AND METHOD FOR ROUNDING A FLOATING-POINT VALUE TO AN INTEGRAL FLOATING-POINT VALUE - Processing circuitry is provided to perform an operation FRINT for rounding a floating-point value to an integral floating-point value. Control circuitry controls the processing circuitry to perform the FRINT operation in response to an FRINT instruction. The processing circuitry includes shifting circuitry for generating a rounding value by shifting a base value, adding circuitry for adding the rounding value to the significand of the floating-point value to generate a sum value, mask generating circuitry for generating a mask for clearing fractional-valued bits of the sum value, and masking circuitry for applying the mask to the sum value to generate the integral floating-point value. | 06-13-2013 |

20130304785 | APPARATUS AND METHOD FOR PERFORMING A CONVERT-TO-INTEGER OPERATION - A data processing apparatus includes processing circuitry for performing a convert-to-integer operation for converting a floating-point value to a rounded two's complement integer value. The convert-to-integer operation uses round-to-nearest, ties away from zero, rounding (RNA rounding). The operation is performed by generating an intermediate value based on the floating-point value, adding a rounding value to the intermediate value to generate a sum value, and outputting the integer-valued bits of the sum value as the rounded two's complement integer value. If the floating-point value is negative, then the intermediate value is generated by inverting the bits without adding a bit value of 1 to a least significant bit of the inverted value. | 11-14-2013 |

20130339412 | DATA PROCESSING APPARATUS AND METHOD - Processing circuitry is provided for performing a shift-round-and-accumulate operation. The operation comprises shifting an input value to generate a shifted value using shifting circuitry, adding the shifted value to an accumulate value using adding circuitry, and performing rounding by adding a rounding value to the sum of the shifted value and the accumulated value using the adding circuitry. The same adding circuitry is used to perform both the addition of the shifted value and the accumulated value and the addition of the rounding value in the same processing cycle. | 12-19-2013 |

20140040334 | DATA PROCESSING APPARATUS AND METHOD FOR REDUCING THE SIZE OF A LOOKUP TABLE - A data processing apparatus is provided with lookup table circuitry for receiving from the processing circuitry an n-bit input data value, and for returning to the processing circuitry an output data value. The lookup table circuitry provides a plurality of entries identifying possible input data values and corresponding output data values, with the plurality of entries being less than 2 | 02-06-2014 |

20150039665 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A NARROWING-AND-ROUNDING ARITHMETIC OPERATION - A processing apparatus supports a narrowing-and-rounding arithmetic operation which generates, in response to two operands each comprising at least one W-bit data element, a result value comprising at least one X-bit result data element, with each X-bit result data element representing a sum or difference of corresponding W-bit data elements of the two operands rounded to an X-bit value (W>X). The arithmetic operation is implemented using a number of N-bit additions (N | 02-05-2015 |