Patent application number | Description | Published |
20080237735 | Hetero-Bimos injection process for non-volatile flash memory - A hetero-BiMOS injection system comprises a MOSFET transistor formed on a substrate and a hetero-bipolar transistor formed within the substrate. The bipolar transistor can be used to inject charge carriers into a floating gate of the MOSFET transistor. This is done by operating the MOSFET transistor to form an inversion layer in its channel region and operating the bipolar transistor to drive minority charge carriers from the substrate into a floating gate of the MOSFET transistor. The substrate provides a silicon emitter and a silicon germanium containing base for the bipolar transistor. The inversion layer provides a silicon collector for the bipolar transistor. | 10-02-2008 |
20090032872 | MULTIPLE OXIDE THICKNESS FOR A SEMICONDUCTOR DEVICE - Techniques associated with providing multiple gate insulator thickness for a semiconductor device are generally described. In one example, an apparatus includes a semiconductor fin having an impurity introduced to at least a first side of the fin, a first oxide having a first thickness coupled with the first side of the fin, and a second oxide having a second thickness coupled with a second side of the fin, the second thickness being different from the first thickness as a result of the impurity introduced to the first side of the fin. | 02-05-2009 |
20090159867 | Phase change memory with layered insulator - A phase change memory may be formed with an insulator made up of two different layers having significantly different thermal conductivities. Pores may be formed within the stack of insulating layers and the pores may be filled with heaters, chalcogenide layers, and electrodes in some embodiments. The use of the two different insulator layers enables embodiments where thermal losses may be reduced and an amorphous region may be maintained along the entire length of the phase change material layer. | 06-25-2009 |
20100072533 | ASYMMETRIC CHANNEL DOPING FOR IMPROVED MEMORY OPERATION FOR FLOATING BODY CELL (FBC) MEMORY - An improved dynamic memory cell using a semiconductor fin or body is described. Asymmetrical doping is used in the channel region, with more dopant under the back gate to improve retention without significantly increasing read voltage. | 03-25-2010 |
20100165772 | Self aligned back-gate for floating body cell memory erase - In some embodiments all cells within a word-line of a floating body cell memory are erased. A back-gate of the floating body cell memory is self-aligned with the word line, and the erasing is performed using a back-gate bias. Other embodiments are described and claimed. | 07-01-2010 |
20120153412 | WRITE CURRENT REDUCTION IN SPIN TRANSFER TORQUE MEMORY DEVICES - The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element. | 06-21-2012 |
20120267721 | FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS - A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. | 10-25-2012 |
20130336045 | SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE WITH HALF-METAL AND METHOD TO WRITE AND READ THE DEVICE - Spin transfer torque memory (STTM) devices with half-metals and methods to write and read the devices are described. For example, a magnetic tunneling junction includes a free magnetic layer, a fixed magnetic layer, and a dielectric layer disposed between the free magnetic layer and the fixed magnetic layer. One or both of the free magnetic layer and the fixed magnetic layer includes a half-metal material at an interface with the dielectric layer. | 12-19-2013 |
20140008602 | THERMAL ISOLATION IN MEMORY CELLS - Thermal isolation in memory cells is described herein. A number of embodiments include a storage element, a selector device formed in series with the storage element, and an electrode between the storage element and the selector device, wherein the electrode comprises an electrode material having a thermal conductivity of less than 0.15 Watts per Kelvin-centimeter (W/K-cm). | 01-09-2014 |
20140084398 | PERPENDICULAR MTJ STACKS WITH MAGNETIC ANISOTROPY ENHANCING LAYER AND CRYSTALLIZATION BARRIER LAYER - Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer. | 03-27-2014 |
20140167191 | METHOD FOR REDUCING SIZE AND CENTER POSITIONING OF MAGNETIC MEMORY ELEMENT CONTACTS - A method of centering a contact on a layer of a magnetic memory device. In one embodiment, a spacers is formed in an opening surrounding the upper layer and the contact is formed within the spacer. The spacer is formed from an anisotropically etched conformal layer deposited on an upper surface and into the opening. | 06-19-2014 |
20140175583 | PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE HAVING OFFSET CELLS AND METHOD TO FORM SAME - Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device. | 06-26-2014 |
20140177326 | ELECTRIC FIELD ENHANCED SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE - Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer. | 06-26-2014 |
20140204661 | MEMORY WITH ELEMENTS HAVING TWO STACKED MAGNETIC TUNNELING JUNCTION (MTJ) DEVICES - A magnetic memory having memory elements each with two magnetic tunneling junction (MTJ) devices is disclosed. The devices in each element are differentially programmed with complementary data. The devices for each element are stacked one above the other so that the element requires no more substrate area than a single MTJ device. | 07-24-2014 |
20140209892 | SELECTOR FOR LOW VOLTAGE EMBEDDED MEMORY - Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is configured with a bitcell having a memory element and a selector element serially connected between an intersection of a wordline and bitline. The selector element can be implemented, for instance, with any number of crystalline materials that exhibit an S-shaped current-voltage (IV) curve, or that otherwise enables a snapback in the selector voltage after the threshold criteria is exceeded. The snapback of the selector is effectively exploited to accommodate the ON-state voltage of the selector under a given maximum supply voltage, wherein without the snapback, the ON-state voltage would exceed that maximum supply voltage. In some example embodiments, the maximum supply voltage is less than 1 volt (e.g., 0.9 volts or less). | 07-31-2014 |
20140299953 | WRITE CURRENT REDUCTION IN SPIN TRANSFER TORQUE MEMORY DEVICES - The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element. | 10-09-2014 |
20140329337 | PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE HAVING OFFSET CELLS AND METHOD TO FORM SAME - Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device. | 11-06-2014 |
20140349415 | PERPENDICULAR MTJ STACKS WITH MAGNETIC ANISOTROPY ENHANCING LAYER AND CRYSTALLIZATION BARRIER LAYER - Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer. | 11-27-2014 |