Patent application number | Description | Published |
20080243453 | CAPACITANCE MODELING - A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (ε | 10-02-2008 |
20080244485 | CAPACITANCE MODELING - A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-clip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (∈ | 10-02-2008 |
20080297261 | Circuits and Methods for Implementing Transformer-Coupled Amplifiers at Millimeter Wave Frequencies - Circuits and methods are provided for building integrated transformer-coupled amplifiers with on-chip transformers that are designed to resonate or otherwise tune parasitic capacitances to achieve frequency tuning of amplifiers at millimeter wave operating frequencies. | 12-04-2008 |
20090150848 | Topologies and Methodologies for AMS Integrated Circuit Design - A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines. | 06-11-2009 |
20090158227 | METHOD AND SYSTEM FOR CALCULATING HIGH FREQUENCY LIMIT CAPACITANCE AND INDUCTANCE FOR COPLANAR ON-CHIP STRUCTURE - Capacitance and inductance expressions used for modeling critical on-chip metal interconnects. A method for calculating high frequency limit capacitances C | 06-18-2009 |
20100013459 | CIRCUITS AND METHODS FOR HIGH-EFFICIENCY ON-CHIP POWER DETECTION - Power detector integrally formed within a printed transmission line to capacitively couple a portion of signal power propagating on the printed transmission line and a power detector circuit that receives coupled power output from the power detector to detect a power level of the signal power. The power detector is designed such that capacitance of the coupling capacitor is absorbed into a distributed capacitance of the transmission line to maintain continuity of a characteristic impedance of the transmission line. | 01-21-2010 |
20110072408 | METHOD AND SYSTEM FOR DESIGN AND MODELING OF TRANSMISSION LINES - A method and system for design and modeling of transmission lines are provided. The method includes providing a set of models of core structures ( | 03-24-2011 |
20110179392 | LAYOUT DETERMINING FOR WIDE WIRE ON-CHIP INTERCONNECT LINES - A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology. | 07-21-2011 |
20120091342 | MONOLITHIC PASSIVE THz DETECTOR WITH ENERGY CONCENTRATION ON SUB-PIXEL SUSPENDED MEMS THREMAL SENSOR - A THz radiation detector comprising a plurality of antenna arms separated from a suspended platform by an isolating thermal air gap. The detector functions to concentrate THz radiation energy into the smaller suspended MEMS platform (e.g., membrane) upon which a thermal sensor element is located. The THz photon energy is converted into electrical energy by means of a pixilated antenna using capacitive coupling in order to couple this focused energy across the thermally isolated air gap and onto the suspended membrane on which the thermal sensor is located. | 04-19-2012 |
20130082802 | STRUCTURE AND COMPACT MODELING OF VARIABLE TRANSMISSION LINES - A novel and useful fabricated variable transmission line that is tuned digitally is presented. Digital tuning of the variable transmission line enables the compensation of process variation in both the active and passive devices of the RF design. Along with several embodiments of the variable transmission line, the present invention also provides a method of compact modeling of the variable transmission line. The variable transmission line structure and compact modeling enables circuit level simulation using a parametric device that in one embodiment can be included as an integral part of a silicon foundry design kit. | 04-04-2013 |
20130194042 | Multi-Stage Amplifier Using Tunable Transmission Lines and Frequency Response Calibration of Same - A multi-stage amplifier is provided that uses tunable transmission lines, as well as a calibration method for the multi-stage amplifiers. A multi-stage amplifier, comprises a plurality of tunable amplification stages, wherein each of the tunable amplification stages comprises a tunable resonator based on a transmission line having a tunable element. The tunable elements may vary a capacitance or an inductance to tune a frequency of an applied signal. A calibration method is provided for a multi-stage amplifier having a plurality of transmission lines, an input stage and an output stage. The multi-stage amplifier is calibrated by generating a signal to determine a frequency for a substantially maximum power; generating an error signal by comparing the frequency for the substantially maximum power with a desired frequency; varying a digital control code applied to each of the tunable transmission lines, input stage and output stage until the error signal satisfies predefined criteria. | 08-01-2013 |
20130318490 | METHOD AND SYSTEM FOR DESIGN AND MODELING OF VERTICAL INTERCONNECTS FOR 3DI APPLICATIONS - A system and method for design and modeling of vertical interconnects for 3DI applications. A design and modeling methodology of vertical interconnects for 3DI applications includes models that represent the frequency dependent behavior of vertical interconnects by means of multi-segment RLC scalable filter networks. The networks allow for accuracy versus computation efficiency tradeoffs, while maintaining correct asymptotic behavior at both high and low frequency limits. In the framework of the model it is shown that a major effect is pronounced frequency dependent silicon substrate induced dispersion and loss effects, which is considered in through silicon via (TSV) parallel Y-element parameters, including capacitance and conductance. | 11-28-2013 |
20140049934 | SLAB INDUCTOR DEVICE PROVIDING EFFICIENT ON-CHIP SUPPLY VOLTAGE CONVERSION AND REGULATION - A voltage conversion circuit such as a buck regulator circuit has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches. The voltage conversion circuit can also include means to reduce or cancel a detrimental effect of other wires on same chip, such as a power grid, that conduct a return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor. | 02-20-2014 |