Patent application number | Description | Published |
20080267183 | Infiniband Multicast Operation in an LPAR Environment - A method, computer program product, and data processing system for providing system-area network (SAN) multicasting functionality in a logically partitioned (LPAR) data processing system in which a channel adapter is shared among a plurality of logical partitions is disclosed. A preferred embodiment of the present invention allows LPAR “hypervisor” firmware to assume the responsibility for multicast protocol handling and distribution of packets among logical partitions. | 10-30-2008 |
20110320653 | SYSTEM AND METHOD FOR ROUTING I/O EXPANSION REQUESTS AND RESPONSES IN A PCIE ARCHITECTURE - A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters at I/O adapter addresses, the I/O hub including logic for implementing a method comprising receiving requests from the plurality of I/O adapters, storing the I/O adapter addresses of a requester along with their corresponding target recipient addresses and operation codes, receiving a response from a responder, the response indicating that a request has been completed, determining that the response is in a format other than a format supported by the I/O bus, transforming the response into the format supported by the I/O bus, locating a stored I/O adapter address having a corresponding target recipient address that matches the responder address and a corresponding operation code that matches the responder operation code, and transmitting the response to the stored I/O adapter address. | 12-29-2011 |
20110320666 | INPUT/OUTPUT (I/O) EXPANSION RESPONSE PROCESSING IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) ENVIRONMENT - A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters, the I/O hub including logic for implementing a method comprising receiving a request from a requester to perform an operation on one of the plurality of I/O adapters. The method further comprising determining that the request is in a format other than a format supported by the I/O bus, determining that the requester requires a completion response for the request, transforming the request into the format supported by the I/O bus, transmitting the request to the I/O adapter, receiving the completion response from the I/O adapter, the completion response comprising an indicator that the request has been completed, the completion response in the format supported by the I/O bus and transmitting the completion response to the requester. | 12-29-2011 |
20110320674 | UPBOUND INPUT/OUTPUT EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIE ARCHITECTURE - A system for implementing non-standard I/O adapters in a standardized input/output (I/O) architecture, the system comprising an I/O adapter communicatively coupled to an I/O hub via an I/O bus, the I/O adapter communicating in a first protocol, the I/O bus communicating in a second protocol different than the first protocol, and the I/O adapter including logic for implementing a method comprising initiating a first request to perform an operation on a host system, the first request formatted for the first protocol and comprising data required to process the first request, and creating a second request responsive to the first request, the second request comprising a header and formatted according to the second protocol, the creating comprising storing the data required to process the first request in the header of the second request. The method further comprising sending the second request to the host system. | 12-29-2011 |
20110320675 | SYSTEM AND METHOD FOR DOWNBOUND I/O EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIe ARCHITECTURE - A system for implementing non-standard I/O adapters in a standardized I/O architecture, the system comprising an I/O hub communicatively coupled to an I/O bus and at least one I/O adapter, the I/O hub including logic for implementing a method, the method comprising receiving a request to perform an operation on the I/O adapter from a requester at a requester address, the I/O adapter at a destination address, determining that the request is in a format other than a format supported by the I/O bus, the I/O bus expecting a requester identifier at a first location in a header of the request, reformatting the request into the format supported by the I/O bus, the reformatting comprising storing the requester address, the destination address and an operation code at the first location in the header of the reformatted request, and sending the reformatted request to the I/O adapter. | 12-29-2011 |
20110320861 | SWITCH FAILOVER CONTROL IN A MULTIPROCESSOR COMPUTER SYSTEM - A system and a method for failover control comprising: maintaining a primary device table entry (DTE) in a first table activated for a first adapter in communication with a first processor node having a first root complex via a first switch assembly and maintaining a secondary DTE in standby for a second adapter in communication with a second processor node having a second root complex via a second switch assembly; maintaining a primary DTE in a second table activated for the second adapter and maintaining a secondary DTE in standby for the first adapter; and upon a failover, updating the secondary DTE in the first table as an active entry for the second adapter and forming a path to enable traffic to route from the second adapter through the second switch assembly over to the first switch assembly and up to the first root complex of the first processor node. | 12-29-2011 |
20110320887 | SCALABLE I/O ADAPTER FUNCTION LEVEL ERROR DETECTION, ISOLATION, AND REPORTING - A system for implementing scalable input/output (I/O) function level error detection, isolation, and reporting, the system comprising, an I/O hub communicatively coupled to a computer processor, system memory and at least one I/O adapter, the at least one I/O adapter include a function and the I/O hub including logic for implementing a method. The method comprising detecting an error in a communication initiated between the function and the system memory, the communication including an I/O request from an application. The method further comprising preventing future communication between the one function and the system memory in response to the detecting. The method additionally comprising notifying the application that the error in communication occurred in response to the detecting. | 12-29-2011 |
20110320892 | MEMORY ERROR ISOLATION AND RECOVERY IN A MULTIPROCESSOR COMPUTER SYSTEM - A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error. | 12-29-2011 |
20130073759 | UPBOUND INPUT/OUTPUT EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIE ARCHITECTURE - Embodiments of the invention relate to non-standard I/O adapters in a standardized input/output (I/O) architecture. An aspect of the invention includes initiating a first request to perform an operation on a host system. The first request formatted for a first protocol and including data required to process the first request. A second request is created responsive to the first request, the second request including a header and is formatted according to the second protocol. The creating includes storing the data required to process the first request in the header of the second request. The second request is sent to the host system. | 03-21-2013 |
20130073766 | INPUT/OUTPUT (I/O) EXPANSION RESPONSE PROCESSING IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) ENVIRONMENT - Embodiments of the invention relate to non-standard input/output (I/O) adapters in a standardized I/O architecture. An aspect of the invention includes implementing non-standard I/O adapters in a standardized I/O architecture. A request is received at an I/O adapter from a requester to perform an operation on one of the I/O adapters. It is determined that the request is in a format other than a format supported by an I/O bus and that the requester requires a completion response for the request. The request is transformed into the format supported by the I/O bus, and is transmitted to the I/O adapter. The completion response is received from the I/O adapter, and includes an indicator that the request has been completed. The completion response is in the format supported by the I/O bus. The completion response is transmitted to the requester. | 03-21-2013 |
20130073767 | INPUT/OUTPUT (I/O) EXPANSION RESPONSE PROCESSING IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) ENVIRONMENT - A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters, the I/O hub including logic for implementing a method comprising receiving a request from a requester to perform an operation on one of the plurality of I/O adapters. The method further comprising determining that the request is in a format other than a format supported by the I/O bus, determining that the requester requires a completion response for the request, transforming the request into the format supported by the I/O bus, transmitting the request to the I/O adapter, receiving the completion response from the I/O adapter, the completion response comprising an indicator that the request has been completed, the completion response in the format supported by the I/O bus and transmitting the completion response to the requester. | 03-21-2013 |
20130086435 | SCALABLE I/O ADAPTER FUNCTION LEVEL ERROR DETECTION, ISOLATION, AND REPORTING - Embodiments of the invention relate to scalable input/output (I/O) function level error detection, isolation, and reporting. An aspect of the invention includes detecting an error in a communication initiated between the function and a system memory, the communication including an I/O request from an application. Future communication is prevented between the one function and the system memory in response to the detecting. The application is notified that the error in communication occurred in response to the detecting. | 04-04-2013 |