Patent application number | Description | Published |
20130258767 | PHASE-CHANGE MEMORY CELL - A phase-change memory cell includes a phase change material; a reference electrical terminal disposed on first side of the phase change material; first and second electrical terminals disposed on a second side of the phase change material; the phase-change material configured to be reversibly transformable between an amorphous phase and a crystalline phase, in response to a phase-altering electrical signal applied to the phase-change material via the reference electrical terminal and one or more of the first and second electrical terminals; a resistance measurement unit configured to measure a respective electrical resistance between each of the first and electrical terminals and the reference electrical terminal; and a mathematical operation unit configured to determine a mathematical relation between the respective electrical resistances measured between each of the electrical terminals and the reference electrical terminal. | 10-03-2013 |
20130322165 | PROGRAMMING OF GATED PHASE-CHANGE MEMORY CELLS - A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧2 programmable cell-states including an amorphous RESET state and at least one crystalline state includes applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance. | 12-05-2013 |
20130322166 | MEMORY APPARATUS WITH GATED PHASE-CHANGE MEMORY CELLS - A memory apparatus includes a plurality of gated phase-change memory cells having s≧2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; and a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming of the addressed cell only. | 12-05-2013 |
20130322167 | PROGRAMMING OF GATED PHASE-CHANGE MEMORY CELLS - A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧2 programmable cell-states including an amorphous RESET state and at least one crystalline state includes applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance. | 12-05-2013 |
20130322168 | MEMORY APPARATUS WITH GATED PHASE-CHANGE MEMORY CELLS - A memory apparatus includes a plurality of gated phase-change memory cells having s≧2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; and a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming of the addressed cell only. | 12-05-2013 |
20140061580 | SEMICONDUCTOR STACK INCORPORATING PHASE CHANGE MATERIAL - A semiconductor stack for performing at least a logic operation includes adjacent layers arranged in a stacked configuration with each layer comprising at least a phase-change memory cell in which a phase-change material is provided between a heater electrical terminal and at least two further heater electrical terminals, the phase-change material between the heater electrical terminal and each of the two further heater electrical terminals being operable in one of at least two reversibly transformable phases, an amorphous phase and a crystalline phase; wherein the semiconductor stack, when in use, is configurable to store information by way of an electrical resistance of the phase of the phase-change material between each heater electrical terminal and each of the two further heater electrical terminals in each layer, and the logic operation is performed on the basis of the information stored in the adjacent layers. | 03-06-2014 |
20140063932 | SEMICONDUCTOR STACK INCORPORATING PHASE CHANGE MATERIAL - A semiconductor stack for performing at least a logic operation includes adjacent layers arranged in a stacked configuration with each layer comprising at least a phase-change memory cell in which a phase-change material is provided between a heater electrical terminal and at least two further heater electrical terminals, the phase-change material between the heater electrical terminal and each of the two further heater electrical terminals being operable in one of at least two reversibly transformable phases, an amorphous phase and a crystalline phase; wherein the semiconductor stack, when in use, is configurable to store information by way of an electrical resistance of the phase of the phase-change material between each heater electrical terminal and each of the two further heater electrical terminals in each layer, and the logic operation is performed on the basis of the information stored in the adjacent layers. | 03-06-2014 |
20150302921 | DEVICE AND METHOD FOR DETERMINING A CELL LEVEL OF A RESISTIVE MEMORY CELL - A device for determining an actual level of a resistive memory cell having a plurality of programmable levels is suggested. The device comprises an estimator unit and a detection unit. The estimator unit is adapted to receive a time input signal and a temperature input signal and to estimate changes of a read-out signal of the levels of the resistive memory cell based on a time and temperature dependent model of the resistance changes, the received time input signal and the received temperature input signal. The detection unit is adapted to receive an actual read-out signal from the resistive memory cell and the estimated changes from the estimator unit. Further, the detection unit is adapted to determine the actual level of the resistive memory cell based on the received read-out signal and the received estimated changes. | 10-22-2015 |