Patent application number | Description | Published |
20090268528 | Semiconductor memory device and access method thereof - Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time. | 10-29-2009 |
20120063242 | DATA RECEIVER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A data receiver in a memory device includes an integration unit, a sense amplification unit and a latch unit. The integration unit integrates a data signal to generate a first equalization signal in response to a sampling feedback signal. The data signal includes a plurality of data that are sequentially received. The sense amplification unit senses the first equalization signal to generate a second equalization signal in response to a sensing feedback signal. The latch unit latches the second equalization signal to generate a sampling data signal | 03-15-2012 |
20120066622 | METHOD, APPARATUS, AND SOFTWARE FOR DISPLAYING DATA OBJECTS - A method, apparatus, and software for displaying data objects. The method, apparatus, and software includes arranging data objects into groups, selecting representative data objects from the groups of the data objects, and upon receiving a zoom-out instruction, zooming out all the data objects except for the representative data objects. | 03-15-2012 |
20120089748 | METHOD OF ENABLING SYNCHRONIZATION BETWEEN DEVICES, USER DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM THEREOF - A method, user device, and computer-readable storage medium enable synchronization between devices. The method includes connecting a second device to a first device, requesting the first device to transform data to be received by the second device and disconnecting the second device to the first device, re-connecting the second device to the first device in response to the occurrence of a first event set at the second device, and receiving the transformed data from the firs device. | 04-12-2012 |
20120127810 | SEMICONDUCTOR MEMORY DEVICE AND ACCESS METHOD THEREOF - Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time. | 05-24-2012 |
20130117602 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS - In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line. | 05-09-2013 |
20130117615 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS - In one embodiment, the memory device includes a memory cell array, to data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells. | 05-09-2013 |
20130117636 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS - In one embodiment, the memory device includes a memory cell array, a data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells. | 05-09-2013 |
20130120629 | PHOTOGRAPHING APPARATUS AND PHOTOGRAPHING METHOD - A photographing apparatus including a main body; an imaging unit installed in the main body configured to convert light incident on a subject into a signal representing an image; a first display unit comprising a first region formed of a transparent material, wherein the first region is configured to transmit light incident to the subject passing through the first region and configured to display the image overlapped with the transmitted light if a signal is applied, and disposed on the main body to be movable between a protruding position where the first region protrudes from the main body and a receiving position where the first region is received in the main body; and a control unit installed in the main body configured to control the imaging unit, and configured to apply the signal to the first display unit to display the image overlapped with the transmitted light. | 05-16-2013 |
20140025880 | SEMICONDUCTOR MEMORY CELL ARRAY HAVING FAST ARRAY AREA AND SEMICONDUCTOR MEMORY INCLUDING THE SAME - A semiconductor memory cell array is provided which includes a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed different from the first operating speed. The first and second memory cell array areas are accessed by addressing of a DRAM controller. | 01-23-2014 |
20140032826 | METHOD OF TRAINING MEMORY CORE AND MEMORY SYSTEM - A method of training a memory device included in a memory system is provided. The method includes testing memory core parameters for a memory core of the memory device during a booting-up sequence of the memory system; determining trimmed memory core parameters based on the test results; storing the determined trimmed memory core parameters; and applying the trimmed memory core parameter to the memory device during a normal operation of the memory device. | 01-30-2014 |
20140089574 | SEMICONDUCTOR MEMORY DEVICE STORING MEMORY CHARACTERISTIC INFORMATION, MEMORY MODULE AND MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD OF THE SAME - A semiconductor memory device storing memory characteristic information, a memory module including the semiconductor memory device, a memory system, and an operating method of the semiconductor memory device. The semiconductor memory device may include a cell array including a plurality of areas; a command decoder configured to decode a command and generate an internal command; and an information storage unit configured to store characteristic information of at least one of the plurality of areas. When a first command and a first row address accompanying the first command are received, characteristic information of an area corresponding to the first row address is provided to an outside. | 03-27-2014 |
20140101535 | MULTI-DISPLAY APPARATUS AND METHOD OF CONTROLLING DISPLAY THEREOF - A multi-display apparatus includes a first body configured to have a first display placed therein, a second body configured to have a second display placed therein, a hinge configured to connect the first body and the second body and to rotatably support the first body and the second body, a communicator configured to communicate with a web server when a web browser is executed, a storage configured to store web page data received from the web server, and a controller configured to display, on the first display, a first web browsing screen based on the web page data, and to display, on the second display, when a first object is selected on the first web browsing screen, a second web browsing screen, which is linked with the first object. | 04-10-2014 |
20140101578 | MULTI DISPLAY DEVICE AND CONTROL METHOD THEREOF - A multi display apparatus includes a first body comprising a first display, a second body comprising a second display, a hinge to connect the first and second bodies to each other, a first imaging unit provided on the first body, a second imaging unit provided on the second body, and a controller to recognize a user's gesture using a plurality of images photographed at the first and second imaging units, and perform a corresponding control operation in response to the recognized user gesture. The controller recognizes the user's gesture using a movement of a user object within recognition ranges of the respective imaging units. As a result, the operation of the multi display apparatus can be controlled more easily and conveniently. | 04-10-2014 |
20140203304 | LIGHT-EMITTING DEVICE PACKAGE STRIP AND METHOD FOR MANUFACTURING THE SAME - Provided is a light-emitting device package strip that includes a lead frame strip, a plurality of resin molding products that are injection-molded in the lead frame strip, and runner and gate members that are formed between adjacent resin molding products and on end sides of a line of adjacent resin molding products, each runner and gate member having a smaller thickness than a thickness of the resin molding products to facilitate cutting thereof. | 07-24-2014 |
20140219036 | EQUALIZER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal. | 08-07-2014 |
20140241093 | DEVICES, SYSTEMS AND METHODS WITH IMPROVED REFRESH ADDRESS GENERATION - A refresh address generator may include a lookup table including a first portion storing a first group of addresses associated with a first data retention time, and a second portion storing a second group of addresses associated with a second data retention time different from the first data retention time, wherein the addresses of the first portion are more frequently accessed than the addresses of the second portion to refresh the memory cells corresponding to the addresses. Systems and methods may also implement such refresh address generation. | 08-28-2014 |