Patent application number | Description | Published |
20090049227 | AVOIDING FAILURE OF AN INITIAL PROGRAM LOAD IN A LOGICAL PARTITION OF A DATA STORAGE SYSTEM - An initial program load (IPL) of a logical partition (LPAR) is managed by establishing a logical path to the LPAR from a storage controller. When a notice is received by the storage controller from the LPAR that the IPL has commenced, the LPAR address is stored in a data structure. After the storage controller initiates a pack change state interrupt, the stored address is compared with the addresses in a list of all LPARS to which the interrupt is directed. If the list of addresses includes the stored address, the stored address is removed from the list. Thus, the pack change state interrupt is transmitted only to the addresses in the list, leaving the LPAR to complete the IPL without interruption. After the storage controller receives a notice from the LPAR that the IPL has completed, the address of the LPAR is removed from the data structure. | 02-19-2009 |
20090049228 | AVOIDING FAILURE OF AN INITIAL PROGRAM LOAD IN A LOGICAL PARTITION OF A DATA STORAGE SYSTEM - An initial program load (IPL) of a logical partition (LPAR) is managed by establishing a logical path to the LPAR from a storage controller. When a notice is received by the storage controller from the LPAR that the IPL has commenced, the LPAR address is stored in a data structure. After the storage controller initiates a pack change state interrupt, the stored address is compared with the addresses in a list of all LPARS to which the interrupt is directed. If the list of addresses includes the stored address, the stored address is removed from the list. Thus, the pack change state interrupt is transmitted only to the addresses in the list, leaving the LPAR to complete the IPL without interruption. After the storage controller receives a notice from the LPAR that the IPL has completed, the address of the LPAR is removed from the data structure. | 02-19-2009 |
20090049456 | LIMITING RECEIPT OF UNSOLICITED EVENTS BY A LOGICAL PARTITION IN A DATA STORAGE SYSTEM - A logical partition (LPAR) is managed in a data processing system by performing an initial program load (IPL), commencing execution of an application on the LPAR and selecting from a plurality of unsolicited events of which the application is to receive notice. A command is transmitted to a storage controller indicating the identity of the selected unsolicited events, wherein the storage controller will store the information in a data structure. Upon the later occurrence of an unsolicited event, the storage controller will transmit to the LPAR only notices of the selected unsolicited events. | 02-19-2009 |
20090049457 | LIMITING RECEIPT OF UNSOLICITED EVENTS BY A LOGICAL PARTITION IN A DATA STORAGE SYSTEM - A logical partition (LPAR) is managed in a data processing system by performing an initial program load (IPL), commencing execution of an application on the LPAR and selecting from a plurality of unsolicited events of which the application is to receive notice. A command is transmitted to a storage controller indicating the identity of the selected unsolicited events, wherein the storage controller will store the information in a data structure. Upon the later occurrence of an unsolicited event, the storage controller will transmit to the LPAR only notices of the selected unsolicited events. | 02-19-2009 |
20090193429 | METHOD TO IDENTIFY UNIQUE HOST APPLICATIONS RUNNING WITHIN A STORAGE CONTROLLER - A method for operating a controller includes receiving a command associated with at least one operation, determining a CPU channel path based on the received command, determining a unique job identifier based on the received command, and determining a state based on the received command. In addition, the method includes updating at least one data matrix based on the determined state, unique job identifier and CPU channel path and operating the controller based on the updated data matrix. | 07-30-2009 |
20090241136 | Method to Precondition a Storage Controller for Automated Data Collection Based on Host Input - An FTDC interface with the host or user. The interface can include a command application programming interface (API) or a data storage Command-Line Interface (DS CLI)/Graphical User Interface (GUI). In certain embodiments, the FTDC interface allows a host or user to customize a desired FTDC on a two-tiered system. The first tier is one in which a host/user selects, from a list of conditions, which ones, upon occurrence of those conditions, they would like the controller to perform FTDC. The second tier a second selection such that for each first tier item, the host/user will select the level of FTDC (collection and offloading of logs and/or the forcing and offloading of a statesave). | 09-24-2009 |
20100185895 | FAILURE-SPECIFIC DATA COLLECTION AND RECOVERY FOR ENTERPRISE STORAGE CONTROLLERS - A method, apparatus, and computer program product for handling a failure condition in a storage controller is disclosed. In certain embodiments, a method may include initially detecting a failure condition in a storage controller. The failure condition may be associated with a specific host and a specific storage device connected to the storage controller. The method may further include determining a failure ID associated with the failure condition. Using the failure ID, en entry may be located in a data collection and recovery table. This entry may indicate one or more data collection and/or recovery processes to execute in response to the failure condition. The method may then execute the data collection and/or recovery processes indicated in the entry. While executing the data collection and/or recovery processes, connectivity may be maintained between hosts and storage devices not associated with the failure condition. | 07-22-2010 |
20120011036 | ADVANCED FUNCTION USAGE-BASED BILLING - An apparatus, system, and method for advanced function usage-based billing. One embodiment of the apparatus includes a detection module, a monitoring module, and a billing report module. The detection module detects use of one or more advanced functions on a storage controller. Each advanced function includes a license-based storage function separate from a standard function set. The monitoring module monitors the detected use of the one or more advanced functions on the storage controller. The communication module communicates billable use information to a billing entity. The billable use information is based on the monitored detected use | 01-12-2012 |
20120011328 | ADVANCED FUNCTION MONITORING ON A STORAGE CONTROLLER - An apparatus, system, and method for advanced function monitoring. One embodiment of the apparatus includes an identification module, a detection module, and a monitoring module. The identification module identifies one or more advanced functions for a storage controller. The one or more advanced functions include optional storage functions beyond a standard function set. The detection module detects use of a particular advanced function of the one or more identified advanced functions. The monitoring module monitors the detected use of the particular advanced function on the storage controller according to a monitoring routine. | 01-12-2012 |
20120011514 | GENERATING AN ADVANCED FUNCTION USAGE PLANNING REPORT - An apparatus, system, and method for generating an advanced function usage planning report. One embodiment of the apparatus includes a detection module, a monitoring module, and a planning report module. The detection module detects use of an advanced function on a storage controller. The advanced function includes an optional storage function beyond a standard function set. The monitoring module monitors the use of the advanced function on the storage controller. The planning report module generates a planning report based at least in part on use information from the monitored use of the advanced function. | 01-12-2012 |
20120096304 | Providing Unsolicited Global Disconnect Requests to Users of Storage - A mechanism is provided in a storage control unit in a data processing system for providing unsolicited global disconnect requests to users. The mechanism stores lock control data in the storage control unit. The storage control unit allocates its resources into a plurality of clusters. Responsive to a given user connecting to a given partition that is for a logical subsystem resident on a first cluster within the plurality of clusters, the mechanism sends reflected partition information from the first cluster to a second cluster within the plurality of clusters. Responsive to the first cluster experiencing a failure condition, the mechanism moves control data from one or more logical subsystems from the first cluster to the second cluster and for each logical subsystem that moved from the first logical subsystem to the second logical subsystem and that has reflected partition information, presents unsolicited status to one or more users. | 04-19-2012 |
Patent application number | Description | Published |
20080294826 | APPARATUS AND METHOD TO CONTROL ACCESS TO STORED INFORMATION - A method is disclosed to control access to stored information. The method supplies a control unit in communication with a computing device and in communication with stored information. If the computing device requests access to that stored information, the method determines if access to the stored information is available. When access to the stored information becomes available, then the method reserves a communication pathway interconnecting the control unit and the requesting computing device, thereby disallowing the sending of non-MPLF unsolicited status via that reserved communication pathway, and provides a message to the computing device, using that reserved communication pathway, granting access to the stored information. | 11-27-2008 |
20090013118 | PRIORITIZATION OF INTERRUPTS IN A STORAGE CONTROLLER BASED ON INTERRUPT CONTROL DIRECTIVES RECEIVED FROM HOSTS - A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive. | 01-08-2009 |
20090013119 | PRIORITIZATION OF INTERRUPTS IN A STORAGE CONTROLLER BASED ON INTERRUPT CONTROL DIRECTIVES RECEIVED FROM HOSTS - A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive. | 01-08-2009 |
20090049218 | RETRIEVING LOCK ATTENTION DATA - Provided are techniques for retrieving lock attention data. A group of attention connection paths configured to transmit lock attention interrupts and lock attention data between the host and the control unit are identified. A lock attention interrupt is received from the control unit. In response to receiving the lock attention interrupt, a connection path from the group of attention connection paths is selected and lock attention data is retrieved from the control unit using the selected connection path | 02-19-2009 |
20090177911 | APPARATUS, SYSTEM, AND METHOD TO PREVENT QUEUE STALLING - An apparatus, system, and method are disclosed to prevent queue stalling. The apparatus to prevent queue stalling is provided with a plurality of modules configured to functionally execute the necessary steps of detecting a connection failure on a first logical path, wherein the first logical path is associated with a first entry in a queue, and wherein the first logical path is configured to define a communication path between an entity associated with a first entry in the queue and a queue manager, scanning the queue to identify a second entry associated with a second logical path in response to the connection failure, and advancing the second entry to a position within the queue that is ahead of the first entry. These modules in the described embodiments include a detection module, a scanning module, and an advancing module. | 07-09-2009 |
20100106877 | APPARATUS AND METHOD TO CONTROL ACCESS TO STORED INFORMATION - A method is disclosed to control access to stored information. The method supplies a control unit in communication with a computing device and in communication with stored information. If the computing device requests access to that stored information, the method determines if access to the stored information is available. When access to the stored information becomes available, then the method reserves a communication pathway interconnecting the control unit and the requesting computing device, thereby disallowing the sending of non-MPLF unsolicited status via that reserved communication pathway, and provides a message to the computing device, using that reserved communication pathway, granting access to the stored information. | 04-29-2010 |
Patent application number | Description | Published |
20100306263 | APPARATUSES AND METHODS FOR DETERMINISTIC PATTERN MATCHING - Apparatuses and methods to perform pattern matching are presented. In one embodiment, an apparatus comprises a memory to store a first pattern table comprising information indicative of whether a byte of input data matches a pattern and whether to ignore other matches of the pattern occur in remaining bytes of the input data. The apparatus further comprises one-byte match logic coupled to the memory, to determine, based on the information in the first pattern table, a one-byte match event with respect to the input data. The apparatus further comprises a control unit to filter the other matches of the pattern based on the information of the first pattern table. | 12-02-2010 |
20110145205 | Packet Boundary Spanning Pattern Matching Based At Least In Part Upon History Information - An embodiment may include circuitry to determine, at least in part, based at least in part upon history information, whether one or more reference patterns are present in a data stream in a packet flow. The data stream may span at least one packet boundary in the packet flow. The history information may include a beginning portion of a packet in the data stream, an ending portion of the packet, and another portion of the data stream. The circuitry may overwrite the another portion of the history information with a respective portion of the data stream to be examined by the circuitry depending, at least in part, upon whether the circuitry determines, at least in part, whether the one or more reference patterns are present in the data stream. The respective portion may be relatively closer than the another portion is to a beginning of the data stream. | 06-16-2011 |
20110154169 | SYSTEM, METHOD, AND APPARATUS FOR A SCALABLE PROCESSOR ARCHITECTURE FOR A VARIETY OF STRING PROCESSING APPLICATIONS - Systems, methods, and apparatus for a scalable processor architecture for variety of string processing application are described. In one such apparatus, n input first in, first out (FIFO) buffer stores an input stream. A plurality of memory banks store data from the input stream. A re-configurable controller processes the input stream. And an output FIFO buffer stores the processed input stream. | 06-23-2011 |
20120150887 | PATTERN MATCHING - An embodiment may include circuitry to determine, at least in part, whether one or more reference patterns are present in a data stream in a packet flow. The circuitry may include first pattern matching circuitry communicatively coupled to second pattern matching circuitry. The first pattern matching circuitry may determine, based at least in part upon one or more deterministic pattern matching operations, whether at least one portion of the one or more reference patterns is present in the stream. If the first pattern matching circuitry determines that the at least one portion of the one or more reference patterns is present in the stream, the second pattern matching circuitry may determine, based at least in part upon one or more pattern matching threads, whether at least one other portion of the one or more reference patterns is present in the stream. Many modifications are possible without departing from this embodiment. | 06-14-2012 |
20130074081 | MULTI-THREADED QUEUING SYSTEM FOR PATTERN MATCHING - A multi-threaded processor may support efficient pattern matching techniques. An input data buffer may be provided, which may be shared between a fast path and a slow path. The processor may retire the data units in the input data buffer that is not required and thus avoids copying the data unit used by the slow path. The data management and the execution efficiency may be enhanced as multiple threads may be created to verify potential pattern matches in the input data stream. Also, the threads, which may stall may exit the execution units allowing other threads to run. Further, the problem of state explosion may be avoided by allowing the creation of parallel threads, using the fork instruction, in the slow path. | 03-21-2013 |
Patent application number | Description | Published |
20100268987 | Circuits And Methods For Processors With Multiple Redundancy Techniques For Mitigating Radiation Errors - Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein. | 10-21-2010 |
20100269018 | Method for preventing IP address cheating in dynamica address allocation - Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein. | 10-21-2010 |
20100269022 | Circuits And Methods For Dual Redundant Register Files With Error Detection And Correction Mechanisms - Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein. | 10-21-2010 |
20110261634 | Differential Threshold Voltage Non-Volatile Memory and Related Methods - Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein. | 10-27-2011 |
20110261635 | Differential Threshold Voltage Non-Volatile Memory and Related Methods - Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein. | 10-27-2011 |
20120063189 | LONGEST PREFIX MATCH INTERNET PROTOCOL CONTENT ADDRESSABLE MEMORIES AND RELATED METHODS - Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein. | 03-15-2012 |
20120070158 | FLEXIBLE IDENTIFICATION SYSTEMS AND RELATED METHODS - Embodiments of flexible identification systems are described herein. Other embodiments and related methods are also disclosed herein. | 03-22-2012 |
20120140929 | INTEGRATED CIRCUITS SECURE FROM INVASION AND METHODS OF MANUFACTURING THE SAME - An integrated circuit device that is secure from invasion and related methods are disclosed herein. Other embodiments are also disclosed herein. | 06-07-2012 |
20120230087 | SRAM CIRCUITS FOR CIRCUIT IDENTIFICATION USING A DIGITAL FINGERPRINT - Circuitry that includes static random access memory (SRAM) access circuitry and a group of SRAM memory cells is disclosed. A digital fingerprint of the group of SRAM memory cells is determined by using the SRAM access circuitry to force at least a portion of the group of SRAM memory cells into a metastable state and then releasing the portion of the SRAM memory cells. Each SRAM memory cell that was released then selects one of two stable states and the SRAM access circuitry provides a selection profile based on the selections. The digital fingerprint is based on the selection profile. | 09-13-2012 |
20120242409 | ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR - Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. | 09-27-2012 |
20120278593 | LOW COMPLEXITY OUT-OF-ORDER ISSUE LOGIC USING STATIC CIRCUITS - Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit. | 11-01-2012 |
20120306535 | STRUCTURES AND METHODS FOR DESIGN AUTOMATION OF RADIATION HARDENED TRIPLE MODE REDUNDANT DIGITAL CIRCUITS - The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The | 12-06-2012 |
20120327725 | CIRCUIT DEVICES AND METHODS HAVING ADJUSTABLE TRANSISTOR BODY BIAS - Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed. | 12-27-2012 |
20130111282 | FAST PARALLEL TEST OF SRAM ARRAYS | 05-02-2013 |
20130154739 | ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR - Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. | 06-20-2013 |
20140049286 | SEQUENTIAL STATE ELEMENTS FOR TRIPLE-MODE REDUNDANT STATE MACHINES, RELATED METHODS, AND SYSTEMS - The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM. | 02-20-2014 |
20140077854 | SEQUENTIAL STATE ELEMENTS RADIATION HARDENED BY DESIGN - This disclosure relates generally to sequential state elements (SSEs). More specifically, embodiments of flip-flops are disclosed, along with computerized methods and systems of designing the same. In one embodiment, the flip-flop includes a substrate and subcircuits that are formed on the substrate. The subcircuits provide subfunctions, wherein each of the subcircuits provides at least one of the subfunctions. More specifically, the subfunctions are provided in a sequential logical order by the subcircuits so that the flip-flop provides a flip-flop function. However, the subcircuits are interleaved out of the sequential logical order with respect to a corresponding subfunction provided by each of the subcircuits along a vector defined by the substrate. In this manner, interleaving the subcircuits along the vector of the substrate can provide separation between charge collection nodes without requiring increases in size. Thus, the flip-flop can be more compact and less expensive to manufacture. | 03-20-2014 |
20140119099 | DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS, AND RELATED METHODS - A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region. | 05-01-2014 |
20140204644 | LONGEST PREFIX MATCH INTERNET PROTOCOL CONTENT ADDRESSABLE MEMORIES AND RELATED METHODS - Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein. | 07-24-2014 |
20140331197 | SEQUENTIAL STATE ELEMENTS IN TRIPLE-MODE REDUNDANT (TMR) STATE MACHINES - The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit. | 11-06-2014 |
20150015334 | ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR - Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. | 01-15-2015 |
20150318026 | Integrated Circuit Device Body Bias Circuits and Methods - A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well. | 11-05-2015 |
20150333738 | Integrated Circuit Process and Bias Monitors and Related Methods - An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor. | 11-19-2015 |
20150349775 | Radiation Hardened By Design Digital Input/Output Circuits And Related Methods - Embodiments of radiation hardened by design digital input/output circuits are described herein. Other examples and related methods are also disclosed herein. | 12-03-2015 |
20150363517 | TECHNIQUES FOR GENERATING PHYSICAL LAYOUTS OF IN SILICO MULTI MODE INTEGRATED CIRCUITS - This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing. | 12-17-2015 |
20160028397 | RADIATION HARDENED DIGITAL CIRCUIT - This disclosure relates generally to radiation hardened digital circuits. In one embodiment, a radiation hardened digital circuit includes a delay network and a first Muller C element. The delay network is configured to generate a first delayed clock signal from a global clock signal such that that the first delayed clock signal is delayed with respect to the global clock signal. The first Muller C element is configured to generate a first clock input signal and set the first clock input signal to one of a set of clock states in response to the first delayed clock signal and the global clock signal each being provided in a same one of the set of clock states and is configured to hold the first clock input signal otherwise. Thus, a radiation strike is prevented from causing a soft error in the first clock input signal. | 01-28-2016 |
20160065243 | RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDENED BY DESIGN MICROPROCESSOR - This disclosure relates generally to processors and methods of operating the same. In particular, this disclosure relates to components for correcting soft errors in a processor. In one embodiment, a processor includes an instruction decoder and an exception handler. The instruction decoder is configured to receive one or more soft error correction instructions and decode the one or more soft error correction instructions. Additionally, an exception handler is configured to execute the one or more soft error correction instructions so as to correct one or more soft errors. In this manner, the processor is capable of correcting soft errors that are the result of radiation strikes. | 03-03-2016 |