Patent application number | Description | Published |
20140110823 | CONTACT STRUCTURE - One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example. | 04-24-2014 |
20140239350 | SEMICONDUCTOR DEVICE CONTAINING HEMT AND MISFET AND METHOD OF FORMING THE SAME - A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer. | 08-28-2014 |
20140252534 | METHOD OF MAKING DEEP TRENCH, AND DEVICES FORMED BY THE METHOD - A method for forming a semiconductor device includes providing a semiconductor-on-insulator (SOI) structure, and forming at least one hard mask (HM) layer over the SOI structure. The SOI structure includes an insulator layer and a semiconductor layer over the insulator layer. The method further comprises forming a trench inside the at least one HM layer and the semiconductor layer, and depositing a spacer layer in the trench. The spacer layer comprises a bottom surface portion over the bottom surface of the trench, and a side wall portion along the side wall of the trench. The method further comprises etching the bottom surface portion of the spacer layer while the side wall portion of the spacer layer remains, and etching the insulator layer to extend the trench into the insulator layer. | 09-11-2014 |
20150044008 | Robot Blade Design - The present disclosure relates to a wafer transfer robot having a robot blade that can be used to handle substrates that are patterned on both sides without causing warpage of the substrates. In some embodiments, the wafer transfer robot has a robot blade coupled to a transfer arm that varies a position of the robot blade. The robot blade has a wafer reception area that receives a substrate. Two or more spatially distinct contact points are located at positions along a perimeter of the wafer reception area that provide support to opposing edges of the substrate. The two or more contact points are separated by a cavity in the robot blade. The cavity mitigates contact between a backside of the substrate and the robot blade, while providing support to opposing sides of the substrate to prevent warpage of the substrate. | 02-12-2015 |
20150069539 | Cup-Like Getter Scheme - The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by increasing an area in which a getter layer is deposited, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having one or more residual gases. A cavity is formed within a top surface of the substrate. The cavity has a bottom surface and sidewalls extending from the bottom surface to the top surface. A getter layer, which absorbs the one or more residual gases, is deposited over the substrate at a position extending from the bottom surface of the cavity to a location on the sidewalls. By depositing the getter layer to extend to a location on the sidewalls of the cavity, the area of the substrate that is able to absorb the one or more residual gases is increased. | 03-12-2015 |
20150069574 | INTEGRATED CIRCUIT AND MANUFACTURING AND METHOD THEREOF - A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above. | 03-12-2015 |
20150069581 | NOBLE GAS BOMBARDMENT TO REDUCE SCALLOPS IN BOSCH ETCHING - A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses. | 03-12-2015 |
20150076657 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A novel method for manufacturing a semiconductor device and a semiconductor device are provided. The semiconductor device includes a substrate, a trench capacitor, a contact pad, an inter-layer dielectric (ILD) layer and contact elements. The trench capacitor includes a doped region, a first dielectric layer, a bottom electrode, a second dielectric layer and a top electrode, in which the contact pad is positioned on the doped region. The ILD layer has contact windows, and the contact elements are disposed therein. Because of the presence of the contact pad positioned on the doped region, the thickness of the ILD layer over the top electrode is increased but still satisfying the requirement of the maximum depth limit to the contact windows of etching the ILD layer. | 03-19-2015 |