Patent application number | Description | Published |
20080238197 | MULTI-MODULE CURRENT SHARING SCHEME - A circuit provides multi-module current sharing for circuit modules. The circuit includes an error amplifier having a negative and a positive input and an output. The positive input of the error amplifier is connected to a reference voltage. A buffered differential amplifier has an output connected to the negative input of the error amplifier and a positive and a negative input. A correction current is sourced to the negative input of the buffered differential amplifier. A resistor connected to the negative input of the buffered differential amplifier has a value that controls the amount of current correction applied to the negative input of the buffer differential amplifier by the current correction source. | 10-02-2008 |
20080238392 | CONTROLLER AND DRIVER COMMUNICATION FOR SWITCHING REGULATORS - Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode. | 10-02-2008 |
20080272752 | PULSE ADDING SCHEME FOR SMOOTH PHASE DROPPING AT LIGHT LOAD CONDITIONS FOR MULTIPHASE VOLTAGE REGULATORS - A multiphase regulator which includes an output node developing an output voltage, a feedback circuit determining error of the output voltage and providing a compensation signal indicative thereof, at least three phase circuits coupled in parallel to the output node, and an adaptive controller. Each phase circuit includes a modulation circuit and a switch circuit. Each modulation circuit receives the compensation signal and generates pulses on a corresponding one of the pulse modulation signals. Each switch circuit is coupled to the output node and is controlled by a corresponding pulse modulation signal. The adaptive controller is responsive to a load indication signal, such as indicating a low load condition, and drops operation of at least one of the phase circuits and adds at least one pulse to a pulse modulation signal of each remaining phase circuit. | 11-06-2008 |
20100079175 | PHASE DOUBLER - A phase doubler driver circuit includes a first input for receiving a input PWM drive signal. First control logic generates a first output PWM drive signal and a second output PWM drive signal responsive to the input PWM drive signal. In a first mode of operation, alternating pulses of the input PWM drive are output as the first output PWM drive signal and the second PWM output drive signal respectively. In a second mode of operation, the input PWM drive signal is provided as the first output PWM drive signal when a second phase current associated with the second output PWM drive signal exceeds a first phase current associated with the first output PWM drive signal and the input PWM drive signal is provided as the second output PWM drive signal when the phase current associated with the first output PWM signal exceed the phase current associated with the second output PWM signal. Second control logic adds an offset to a falling edge of the first output PWM drive signal responsive to a difference between a first current associated with the first phase current and an average current and for adding the offset to a falling edge of the second output PWM signal responsive to a difference between a second current associated with the second phase current and the average current, wherein the average current comprises the average of the first current and the second current. Drive circuitry generates drive signals responsive to each of the first output PWM drive signal and the second output PWM drive signal. | 04-01-2010 |
20100171645 | N-BIT ADC READER - An integrated circuit including a single input pin for determining a value associated with a resistor divider. The circuit includes first circuitry for determining a resistor ratio of the resistor divider through the single input pin. A first register stores a first group of bits representing the resistor ratio. The first group of bits comprises the least significant bits of the value. Second circuitry determines an equivalent resistance of the resistor divider through the single input pin. A second register stores a second group of bits representing the equivalent resistance. The second group of bits comprises the most significant bits of the value associated with the resistor divider. | 07-08-2010 |
20100283523 | CONTROLLER AND DRIVER COMMUNICATION FOR SWITCHING REGULATORS - Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three ( | 11-11-2010 |
20100320977 | PULSE ADDING SCHEME FOR SMOOTH PHASE DROPPING AT LIGHT LOAD CONDITIONS FOR MULTIPHASE VOLTAGE REGULATORS - A pulse control system for a multiphase regulator including an error amplifier, a multiphase generator, and an adaptive controller. The error amplifier provides an error signal indicative of output voltage error. The multiphase generator develops modulation pulses for phases based on the error signal. The adaptive controller is responsive to a load indication signal and redirects at least one modulation pulse from a first of phase to a second phase. The load indication signal may be received from a microprocessor indicating a low power mode. The adaptive controller provides a smooth and efficient transition to low load conditions by dropping operation of one or more phases and redirecting modulation pulses to the remaining one or more phases, and reduced phases improve power efficiency for the low load conditions. | 12-23-2010 |
20110133716 | CONTROLLER AND DRIVER COMMUNICATION FOR SWITCHING REGULATORS - Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode. | 06-09-2011 |
20110133717 | CONTROLLER AND DRIVER COMMUNICATION FOR SWITCHING REGULATORS - Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode. | 06-09-2011 |
20110204947 | METHOD AND APPARATUS FOR ADAPTIVELY MODIFYING A PULSE WIDTH OF A PULSE WIDTH MODULATED OUTPUT - Systems, methods, and apparatus for improving steady state operation of a pulse width modulator during transient and soft start events are described herein. An apparatus can include a phase component configured to adaptively modify a pulse width of a first pulse width modulated (PWM) output signal based on a pulse width of a PWM input signal. Further, the apparatus can include a power stage component configured to source at least one of a voltage or a current to a load based on the first PWM output signal. In one example, the phase component can be configured to linearly extend the pulse width of the first PWM output signal based on the pulse width of the PWM input signal. In another example, the phase component can be configured to adaptively modify the pulse width of the first PWM output signal based on a predetermined maximum pulse width. | 08-25-2011 |
20110241640 | SYSTEM AND METHOD OF INTERMITTENT DIODE BRAKING FOR MULTIPLE PHASE VOLTAGE REGULATOR - A method of operating a regulator controller IC for performing intermittent diode braking for controlling a multiple phase voltage regulator. The method includes receiving at least one signal for detecting repetitive load transients, determining a rate of the repetitive load transients, generating diode braking control signals, each for applying diode braking to a corresponding one of multiple phases for at least one load transient when the repetitive load transients are below a first rate, and controlling the diode braking control signals to drop application of diode braking of at least one phase for at least one load transient when the repetitive load transients are at least the first rate. The method may include rotating the application of diode braking among the phases during successive applications of diode braking. The method may include dropping an increased number of phases for diode braking as the rate of repetitive load transients is increased. | 10-06-2011 |
20140197811 | CURRENT LIMITING SCHEME FOR A CONVERTER - A modulator configured to control switching of current through an inductor of a converter according to a current limiting scheme while converting an input voltage to an output voltage, which includes a current limit generator and a comparator network. The current limit generator is configured to provide a periodic ramping current limit value based on either the input voltage or the output voltage, an inductance of the inductor, a timing signal, and a predetermined maximum output current of the boost converter. The comparator network is configured to provide a switch control signal to control switching of current through the inductor by comparing a current sense value indicative of a current through the inductor with a lesser of a compensation error value and the periodic ramping current limit value. The converter may be configured as a peak current mode control converter in either boost or buck mode. | 07-17-2014 |