Patent application number | Description | Published |
20090257287 | PROGRAMMABLE BIAS CIRCUIT ARCHITECTURE FOR A DIGITAL DATA/CLOCK RECEIVER - Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture for a computer processor includes a first linear receiver stage configured to receive a first input, a second input, and a first bias voltage. The first linear receiver stage is configured to generate a first differential output signal in response to a comparison between the first input and the second input. The first differential output signal has a specified programmable voltage swing that is influenced by the first bias voltage. The receiver architecture also includes a first programmable bias circuit coupled to the first linear receiver stage. The first programmable bias circuit is configured to generate the first bias voltage. | 10-15-2009 |
20090257294 | PROGRAMMABLE LINEAR RECEIVER FOR DIGITAL DATA CLOCK SIGNALS - Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes three linear receiver stages coupled in series. The first stage receives a differential data strobe (DQS) input signal associated with a plurality of data (DQ) signals, and the first stage has a first programmable swing voltage associated therewith. The second stage has a programmable shift voltage associated therewith, and the third stage has a second programmable swing voltage associated therewith. The receiver architecture also includes a programming architecture coupled to the first stage, the second stage, and the third stage. The programming architecture is configured to set the first programmable swing voltage, the programmable shift voltage, and the second programmable swing voltage. | 10-15-2009 |
20090259872 | PROGRAMMABLE DATA SAMPLING RECEIVER FOR DIGITAL DATA SIGNALS - Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes a linear receiver portion having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver portion is configured to compare the DQ signal to the reference voltage, and to generate the differential output signal in response to the comparison. A sense amplifier portion is coupled to the linear receiver portion. The sense amplifier portion has input nodes connected to the output nodes of the linear receiver portion, and an output node for a binary output signal having voltage characteristics compatible with the computer processor. The sense amplifier portion is configured to transform the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver portion, the programming architecture being configured to set operating characteristics of the linear receiver portion. | 10-15-2009 |
Patent application number | Description | Published |
20080304423 | Network traffic monitoring in a server network environment - Systems, methods, and other embodiments associated with monitoring a server port in a server network environment are described. In one embodiment, a graphical user interface (GUI) allows server port(s) to be selected for monitoring. The GUI also allows for an uplink port to be selected, where the uplink port is a port that may be connected to a network analyzer. In response to the selections, a virtual local area network (VLAN) is created to establish communication between the selected server port(s) and the selected uplink port. Network traffic that passes through the selected server port(s) can then be duplicated and transmitted through the VLAN to the selected uplink port to be monitored and analyzed by a network analyzer connected to the uplink port. | 12-11-2008 |
20080304519 | METHOD FOR ETHERNET POWER SAVINGS ON LINK AGGREGATED GROUPS - This invention provides the ability to significantly lower the power consumed by a group of Ethernet links when organized in a Link Aggregation Group. When the server or switch senses low bandwidth utilization across multiple links in the group, it will negotiate the transition of un-necessary links to a lower power state. When the bandwidth requirements increases, the algorithm will quickly re-establish links and distribute the Ethernet traffic across the multiple links when necessary. | 12-11-2008 |
20110029669 | Adjustable Server-Transmission Rates Over Fixed-Speed Backplane Connections Within A Multi-Server Enclosure - Embodiments of the present invention are directed to providing configurable transmission rates for devices within a multi-device enclosure, despite common communication media within the multi-device enclosure that would otherwise constrain or fix the transmission rates of the devices. In one embodiment of the present invention, implemented within a virtual-connect manager or other module or device contained in, or associated with, a multi-server enclosure, the virtual-connect manager provides an administrative or management interface through which each server can be assigned a maximum transmission rate. The virtual-connect manager then continuously monitors the transmission rates of servers and/or ports within servers in order to apply back pressure, or flow control, so that the servers and/or ports within servers do not exceed the configured maximum transmission rates. | 02-03-2011 |
20120113870 | CONFIGURATION OF NETWORK LINKS IN A VIRTUAL CONNECTION ENVIRONMENT - A method for establishing connections in a virtual connection environment by passing links, to external systems through a bridge. The bridge participates in the spanning tree, protocol procedure to reach a stable topology. Active bridge connections then behave as a simple pass through to external systems. The virtual connect domain appears to external systems as a single system void of any possible communication loops. | 05-10-2012 |
Patent application number | Description | Published |
20110092898 | MEDICINE INJECTION INTO SKIN WITH HEATER CHIP - A device configured for drug delivery through the skin of a subject, the device comprising a substrate, a proximal side of which is positioned toward the skin of the subject during use; at least one fluid receptacle positioned on the substrate and containing a store of the drug; at least one ejection chamber positioned on the proximal side of the substrate; at least one fluid via fluidly connecting the at least one fluid receptacle with the at least one ejection chamber; a heating element positioned adjacent at least a portion of the at least one ejection chamber, said heating element configured to rapidly heat and vaporize the fluid along that portion of the ejection chamber, causing ejection of fluid therefrom; and logic, wherein the logic is programmable to initiate heating by the heating element. | 04-21-2011 |
20110298092 | DIODES WITH A DOG BONE OR CAP-SHAPED JUNCTION PROFILE TO ENHANCE ESD PERFORMANCE, AND OTHER SUBSTRUCTURES, INTEGRATED CIRCUITS AND PROCESSES OF MANUFACTURE AND TESTING - An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed. | 12-08-2011 |
20120100680 | Low Temperature Implant Scheme to Improve BJT Current Gain - A process of forming an integrated circuit containing an npn BJT and an NMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting n-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the NMOS transistor. A process of forming an integrated circuit containing a pnp BJT and a PMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting p-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the PMOS transistor. A process of forming an integrated circuit containing an implant region by cooling the integrated circuit substrate to 5° C. or colder and implanting atoms, at a specified minimum dose according to species, into the implant region. | 04-26-2012 |
20130065374 | Fluorine Implant Under Isolation Dielectric Structures to Improve Bipolar Transistor Performance and Matching - A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch. | 03-14-2013 |
20130244411 | DIODES WITH A DOG BONE OR CAP-SHAPED JUNCTION PROFILE TO ENHANCE ESD PERFORMANCE, AND OTHER SUBSTRUCTURES, INTEGRATED CIRCUITS AND PROCESSES OF MANUFACTURE AND TESTING - An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed. | 09-19-2013 |