Patent application number | Description | Published |
20080201672 | CASCADED PASS-GATE TEST CIRCUIT WITH INTERPOSED SPLIT-OUTPUT DRIVE DEVICES - A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate. | 08-21-2008 |
20080278992 | INDEPENDENT-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL - Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell. | 11-13-2008 |
20090067223 | COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL - Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters. | 03-12-2009 |
20090302894 | DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC - A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation. | 12-10-2009 |
Patent application number | Description | Published |
20090018787 | APPARATUS AND METHOD FOR DETERMINING THE SLEW RATE OF A SIGNAL PRODUCED BY AN INTEGRATED CIRCUIT - Determining a slew rate of a signal from an integrated circuit under test by comparing the signal with a first reference voltage, comparing the signal with a second reference voltage different from the first reference voltage, generating an output pulse having a pulse width indicative of a slew rate of the signal, and integrating the output pulse over time to generate an output voltage proportional to the pulse width; wherein the output voltage is indicative of the slew rate of the signal produced by the integrated circuit. | 01-15-2009 |
20090091346 | CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS - A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level. | 04-09-2009 |
20090185409 | ENHANCED STATIC RANDOM ACCESS MEMORY STABILITY USING ASYMMETRIC ACCESS TRANSISTORS AND DESIGN STRUCTURE FOR SAME - A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the | 07-23-2009 |
20090189703 | CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS TEMPERATURE INSTABILITY) EFFECT AND/OR PBTI (POSITIVE BIAS TEMPERATURE INSTABILITY) EFFECT - A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates. | 07-30-2009 |
20090190426 | CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM ARRAYS - The circuit includes a static random access memory array having a plurality of cells, in turn having a plurality of devices; as well as a global sensor having at least one output, coupled to the static random access memory array, and configured to sense at least one of global readability and global write-ability. Also included is a decision-making circuit coupled to the at least one output of the global sensor. The decision-making circuit is configured to determine, from the at least one output of the global sensor, whether adaptation signals are required to correct global readability and/or write-ability. An adaptation signal generation block is also included and is coupled to the decision-making circuit and the array, and configured to supply the adaptation signals to the array, responsive to the decision-making circuit determining that the adaptation signals are required. At least the array and the global sensor, and preferably the decision-making circuit and the adaptation signal generation block as well, are implemented on a single integrated circuit chip. An associated method and design structure(s) are also provided. | 07-30-2009 |
20090302354 | High Density Stable Static Random Access Memory - A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer | 12-10-2009 |
20090310430 | METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS - A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level. | 12-17-2009 |
20110173577 | Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields - Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained. | 07-14-2011 |
20120185817 | Enhanced Static Random Access Memory Stability Using Asymmetric Access Transistors and Design Structure for Same - A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein. | 07-19-2012 |
Patent application number | Description | Published |
20090164375 | SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR PERFORMING MASS TRANSIT MERCHANT TRANSACTIONS - Methods, systems and computer program products are provided for enabling access to mass transit systems using a financial transaction instrument including reading an identifier including financial payment information from the financial transaction instrument and determining whether the identifier is stored in a database. Access to a holder of the financial transaction instrument is provided based on the determining. | 06-25-2009 |
20110060687 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ISSUING AND USING DEBIT CARDS - A system, method, and computer program product are used to issue and track debit cards. A system comprises an enrolling system that verifies an enrollee, associates an enrollee's main and overdraft account, and issues a debit card, an authentication system that receives information regarding a requested transaction of a debit card and that receives information regarding the main and overdraft account associated with the debit card and accepts or rejects the requested transaction based thereon, and a settlement system that generates a periodic report of at least one of the transactions, the main account, and the overdraft account. The overdraft account can be a charge or credit account. | 03-10-2011 |
20120109722 | SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR PERFORMING MASS TRANSIT MERCHANT TRANSACTIONS - Methods, systems and computer program products are provided for enabling access to mass transit systems using a financial transaction instrument including reading an identifier including financial payment information from the financial transaction instrument and determining whether the identifier is stored in a database. Access to a holder of the financial transaction instrument is provided based on the determining. | 05-03-2012 |
20120209842 | SYSTEMS AND METHODS FOR GENERATING CUSTOMIZED TRAVEL ITINERARIES - A method for generating a customized travel itinerary is disclosed. The method may comprise associating an individual with a travel sign based upon the results of a travel quiz; associating the individual with a travel location based upon the travel sign and a travel date; and associating the individual with an activity item based upon the travel sign. The method may additionally comprise receiving, by a mobile communication device, a travel itinerary comprising a plurality of travel locations; displaying, by the mobile communication device, a first travel location from the plurality of travel locations prior to a scheduled departure time for the first travel location; and displaying, by the mobile communication device, a second travel location from the plurality of travel locations prior to a scheduled departure time for the second travel location. | 08-16-2012 |
20120226546 | System and Method for Satisfying a Transaction Amount from an Alternative Funding Source - Systems and methods for paying a transaction amount at a point of sale (e.g. a physical point of sale or a virtual point of sale) are disclosed. The systems and methods are configured to monitor transaction information to identify eligible transactions at the point of sale. Where the transaction information conforms to predetermined rules, an indicator of an alternative funding source is provided to a user through a web browser, portable electronic device, or other suitable medium. Moreover, the alternative funding options are presented at substantially the same time as a transaction is being processed at a point of sale. Based on the user's selection, a credit may be applied to the transaction account corresponding with at least a portion of the transaction amount from the alternative funding source. Moreover, the credit associated with the alternative funding source is not communicated to the point of sale or the corresponding merchant, but rather is applied directly to the transaction account associated with the purchase of an item. | 09-06-2012 |
20130054337 | METHODS AND SYSTEMS FOR CONTACTLESS PAYMENTS FOR ONLINE ECOMMERCE CHECKOUT - A process of conducting a contactless payment in an online transaction comprises initiating, at a computer-based system, an online transaction based on a consumer selection, transmitting, from an RF device, consumer information to the computer-based system. The consumer information may provide at least one of shipping information, account information, and billing information for completing the online transaction. Further, the method includes populating a check-out screen with consumer information from the radio frequency device. The consumer is able to confirm the online transaction and associated information prior to submission for processing. In various embodiments of conducting the contactless payment of an online transaction, the RF device may be at least one of a transponder, a mobile phone, a smart phone, or a fob. The contactless-enabled device may at least one of a desktop computer, a laptop computer, a tablet computer, a notebook computer, a mobile phone, or a smart phone. | 02-28-2013 |
20130054412 | METHODS AND SYSTEMS FOR CONTACTLESS PAYMENTS FOR ONLINE ECOMMERCE CHECKOUT - A process of conducting a contactless payment in an online transaction comprises initiating, at a computer-based system, an online transaction based on a consumer selection, transmitting, from an RF device, consumer information to the computer-based system. The consumer information may provide at least one of shipping information, account information, and billing information for completing the online transaction. Further, the method includes populating a check-out screen with consumer information from the radio frequency device. The consumer is able to confirm the online transaction and associated information prior to submission for processing. In various embodiments of conducting the contactless payment of an online transaction, the RF device may be at least one of a transponder, a mobile phone, a smart phone, or a fob. The contactless-enabled device may at least one of a desktop computer, a laptop computer, a tablet computer, a notebook computer, a mobile phone, or a smart phone. | 02-28-2013 |
20130054413 | METHODS AND SYSTEMS FOR CONTACTLESS PAYMENTS - A contactless payment system for merchant transactions (e.g., a restaurant) comprises generating, at the contactless payment system, a total bill of purchases associated with a consumer, associating a unique identifier of a RFID tag or a QR code with the total bill, transmitting the total bill and associated unique identifier to a consumer accessible payment network, and receiving payment from the consumer for satisfaction of the total bill. The consumer submits the payment using a contactless-enabled device, such as a smartphone. The contactless-enabled device may interrogate the RFID tag or read the QR code to receive the unique identifier and a payment network link. Furthermore, the contactless-enabled device submits a payment transaction request to the payment network, where the payment transaction request includes the unique identifier and an account identifier. The payment network receives the payment transaction request and locates the total bill using the unique identifier as a key. | 02-28-2013 |
20130232046 | SYSTEM AND METHOD FOR DEFAULT PAYMENT SETTING - A consumer accesses a secure area of a transaction account website and provides their login information for retail websites. The transaction account issuer or a third party creates a script that logs in to the retail websites on behalf of the consumer and transmits transaction account information associated with the transaction account. The script sets the transaction account as the default payment method for the retail website. The transaction account information may be evergreen, such that whenever the transaction account information changes, the script updates the retail websites. | 09-05-2013 |
20140058857 | SYSTEM AND METHOD FOR SATISFYING A TRANSACTION AMOUNT FROM AN ALTERNATIVE FUNDING SOURCE - Systems and methods for paying a transaction amount at a point of sale (e.g. a physical point of sale or a virtual point of sale) are disclosed. The systems and methods are configured to monitor transaction information to identify eligible transactions at the point of sale. Alternative funding options may be presented at substantially the same time as a transaction is being processed at a point of sale. Based on the user's selection, a credit may be applied to the transaction account corresponding with at least a portion of the transaction amount from the alternative funding source. | 02-27-2014 |
20140201085 | METHODS AND SYSTEMS FOR CONTACTLESS PAYMENTS AT A MERCHANT - A coordination server of a contactless payment system may receive a total bill of purchases for a customer from a merchant point-of-sale terminal, associate the total bill of purchases with a unique identifier of an RFID tag of a check presenter, and receive notification that payment of the total bill of purchases is authorized. The coordination server may receive the unique identifier and payment information from a contactless-enabled device, and transmit the payment information and the total bill to the merchant point-of-sale terminal for transmittal to a merchant acquirer for completion of the transaction under business as usual standards. In one embodiment, the coordination server transmits the payment information and the total bill to a merchant acquirer, which then routes the payment request to an appropriate payment network. In another embodiment, the coordination server transmits the payment information and the total bill directly to the appropriate payment network. | 07-17-2014 |
Patent application number | Description | Published |
20120001293 | SEMICONDUCTOR ON GLASS SUBSTRATE WITH STIFFENING LAYER AND PROCESS OF MAKING THE SAME - A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film. | 01-05-2012 |
20120003813 | OXYGEN PLASMA CONVERSION PROCESS FOR PREPARING A SURFACE FOR BONDING - A process for preparing a surface of a material that is not bondable to make it bondable to the surface of another material. A non-bondable surface of a semiconductor wafer is treated with oxygen plasma to oxidize the surface of the wafer and make the surface smoother, hydrophilic and bondable to the surface of another substrate, such as a glass substrate. The semiconductor wafer may have a barrier layer thereon formed of a material, such as SixNy or SiNxOy that is not bondable to another substrate, such as a glass substrate. In which case, the oxygen plasma treatment converts the surface of the barrier layer to oxide, such as SiO2, smoothing the surface and making the surface hydrophilic and bondable to the surface of another substrate, such as a glass substrate. The converted oxide layer may be stripped from the barrier layer or semiconductor wafer with an acid, in order to remove contamination on the surface of the barrier layer or semiconductor wafer, the stripped surface may undergo a second oxygen plasma treatment to further smooth the surface, and make the surface hydrophilic and bondable to the surface of another substrate | 01-05-2012 |
20130130473 | SEMICONDUCTOR ON GLASS SUBSTRATE WITH STIFFENING LAYER AND PROCESS OF MAKING THE SAME - A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film. | 05-23-2013 |
20130341756 | SEMICONDUCTOR ON GLASS SUBSTRATE WITH STIFFENING LAYER AND PROCESS OF MAKING THE SAME - A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film. | 12-26-2013 |
20140116091 | HIGH-SPEED MICRO-HOLE FABRICATION IN GLASS - A method for fabricating a high-density array of holes in glass comprises providing a glass sheet having a front surface and irradiating the glass sheet with a laser beam so as to produce open holes extending into the glass sheet from the front surface of the glass sheet. The beam creates thermally induced residual stress within the glass around the holes, and after irradiating, the glass sheet is annealed to eliminate or reduce thermal stress caused by the step of irradiating. The glass sheet is then etched to produce the final hole size. Preferably, the glass sheet is also annealed before the step of irradiating, at sufficiently high temperature for a sufficient time to render the glass sheet dimensionally stable during the step of annealing after irradiating. | 05-01-2014 |
20140144772 | HIGH RATE DEPOSITION SYSTEMS AND PROCESSES FOR FORMING HERMETIC BARRIER LAYERS - A method of forming a hermetic barrier layer comprises sputtering a thin film from a sputtering target, wherein the sputtering target includes a sputtering material such as a low T | 05-29-2014 |