Patent application number | Description | Published |
20090026623 | BURIED METAL-SEMICONDUCTOR ALLOY LAYERS AND STRUCTURES AND METHODS FOR FABRICATION THEREOF - A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region. | 01-29-2009 |
20090152590 | METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM DEPOSITS - A method of forming a semiconductor device including forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium, and the second deposit having a second percentage of germanium that is less than the first percentage and supports forming a silicide deposit on the second deposit. A structure is also provided. | 06-18-2009 |
20090315182 | SILICIDE INTERCONNECT STRUCTURE - A method for forming an interconnect structure includes forming a dielectric layer above a first layer having a conductive region defined therein. An opening is defined in the dielectric layer to expose at least a portion of the conductive region. A metal silicide is formed in the opening to define the interconnect structure. A semiconductor device includes a first layer having a conductive region defined therein, a dielectric layer formed above the first layer, and a metal silicide interconnect structure extending through the dielectric layer to communicate with the conductive region. | 12-24-2009 |
20100062597 | Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers - An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. | 03-11-2010 |
20110147809 | FORMING A CARBON CONTAINING LAYER TO FACILITATE SILICIDE STABILITY IN A SILICON GERMANIUM MATERIAL - A method includes forming a silicon germanium layer, forming a layer comprising carbon and silicon on a top surface of the silicon germanium layer, forming a metal layer above the layer comprising carbon and silicon, and performing a thermal treatment to convert at least the layer comprising carbon and silicon to form a metal silicide layer. | 06-23-2011 |
20110241115 | Schottky Junction Source/Drain FET Fabrication Using Sulfur or Flourine Co-Implantation - A Schottky field effect transistor (FET) includes a gate stack located on a silicon on insulator (SOI) layer, the gate stack comprising a gate silicide region; and source/drain silicide regions located in the SOI layer, the source/drain silicide regions comprising and at least one of sulfur and fluorine, wherein an interface comprising arsenic is located between each of the source/drain silicide regions and the SOI layer. A method of forming a contact, the contact comprising a silicide region adjacent to a silicon region, includes co-implanting the silicide region with arsenic and at least one of sulfur and fluorine; and drive-in annealing the co-implanted silicide region to diffuse the arsenic to an interface between the silicide region and the silicon region. | 10-06-2011 |
20110241116 | FET with FUSI Gate and Reduced Source/Drain Contact Resistance - A method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer; forming a fully silicided gate from the gate polysilicon and forming source/drain silicide regions in the silicon layer; implanting the gate silicide and the source/drain silicide with dopants; and performing rapid thermal annealing to form a gate interfacial layer in between the gate silicide and the gate oxide layer, and source/drain interfacial layers between the source/drain silicide regions and the silicon layer. | 10-06-2011 |
20110241213 | Silicide Contact Formation - A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less. | 10-06-2011 |
20110248343 | Schottky FET With All Metal Gate - A method for forming a Schottky field effect transistor (FET) includes forming a gate stack on a silicon substrate, the gate stack comprising a gate polysilicon on top of a gate metal layer; depositing a metal layer over the gate polysilicon and the silicon substrate; annealing the metal layer, the gate polysilicon, and the silicon substrate such that the metal layer fully consumes the gate polysilicon to form a gate silicide and reacts with portions of the silicon substrate to form source/drain silicide regions in the silicon substrate; and in the event a portion of the metal layer does not react with the gate polysilicon or the silicon substrate, removing the unreacted portion of the metal layer. | 10-13-2011 |
20120007181 | Schottky FET Fabricated With Gate Last Process - A method for forming a field effect transistor (FET) includes forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions are located in the top semiconductor layer on either side of the dummy gate; forming a supporting material over the source and drain regions adjacent to the dummy gate; removing the dummy gate to form a gate opening, wherein a channel region of the top semiconductor layer is exposed through the gate opening; thinning the channel region of the top semiconductor layer through the gate opening; and forming gate spacers and a gate in the gate opening over the thinned channel region. | 01-12-2012 |
20120009771 | Implantless Dopant Segregation for Silicide Contacts - A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer. | 01-12-2012 |
20120038048 | STABILIZED NICKEL SILICIDE INTERCONNECTS - A method of forming nickel monosilicide is provided that includes providing a silicon-containing surface, and ion implanting carbon into the silicon-containing surface. | 02-16-2012 |
20120091589 | METHOD TO ELECTRODEPOSIT NICKEL ON SILICON FOR FORMING CONTROLLABLE NICKEL SILICIDE - The present disclosure relates to an improved method of providing a Ni silicide metal contact on a silicon surface by electrodepositing a Ni film on a silicon substrate. The improved method results in a controllable silicide formation wherein the silicide has a uniform thickness. The metal contacts may be incorporated in, for example, CMOS devices, MEM (micro-electro-mechanical) devices, and photovoltaic cells. | 04-19-2012 |
20120112292 | INTERMIXED SILICIDE FOR REDUCTION OF EXTERNAL RESISTANCE IN INTEGRATED CIRCUIT DEVICES - A method for forming an alternate conductive path in semiconductor devices includes forming a silicided contact in a source/drain region adjacent to an extension diffusion region and removing sidewall spacers from a gate structure. A metal layer is formed over a portion of the extension diffusion region in a substrate layer to intermix metal from the metal layer with the portion of the extension region without annealing the metal layer. An unmixed portion of the metal layer is removed. The alternate conductive path is formed on the extension diffusion region with intermixed metal by thermal processing after the unmixed portion of the metal layer has been removed. | 05-10-2012 |
20120190192 | Metal-Semiconductor Intermixed Regions - In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure. | 07-26-2012 |
20120193729 | DEVICES AND METHODS TO OPTIMIZE MATERIALS AND PROPERTIES FOR REPLACEMENT METAL GATE STRUCTURES - Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor. | 08-02-2012 |
20120202345 | METHOD TO ENABLE THE PROCESS AND ENLARGE THE PROCESS WINDOW FOR SILICIDE, GERMANIDE OR GERMANOSILICIDE FORMATION IN STRUCTURES WITH EXTREMELY SMALL DIMENSIONS - Techniques for silicide, germanide or germanosilicide formation in extremely small structures are provided. In one aspect, a method for forming a silicide, germanide or germanosilicide in a three-dimensional silicon, germanium or silicon germanium structure having extremely small dimensions is provided. The method includes the following steps. At least one element is implanted into the structure. At least one metal is deposited onto the structure. The structure is annealed to intersperse the metal within the silicon, germanium or silicon germanium to form the silicide, germanide or germanosilicide wherein the implanted element serves to prevent morphological degradation of the silicide, germanide or germanosilicide. The implanted element can include at least one of carbon, fluorine and silicon. | 08-09-2012 |
20120295439 | Metal-Semiconductor Intermixed Regions - In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure. | 11-22-2012 |
20120299102 | FET with FUSI Gate and Reduced Source/Drain Contact Resistance - A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer. | 11-29-2012 |
20120299104 | SCHOTTKY FET FABRICATED WITH GATE LAST PROCESS - A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate. | 11-29-2012 |
20120326216 | DEVICES AND METHODS TO OPTIMIZE MATERIALS AND PROPERTIES FOR REPLACEMENT METAL GATE STRUCTURES - Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor. | 12-27-2012 |
20120326318 | BURIED METAL-SEMICONDUCTOR ALLOY LAYERS AND STRUCTURES AND METHODS FOR FABRICATION THEREOF - A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region. | 12-27-2012 |
20130020616 | SILICIDED DEVICE WITH SHALLOW IMPURITY REGIONS AT INTERFACE BETWEEN SILICIDE AND STRESSED LINER - A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region. | 01-24-2013 |
20130069124 | MOSFET INTEGRATED CIRCUIT WITH UNIFORMLY THIN SILICIDE LAYER AND METHODS FOR ITS MANUFACTURE - An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches. | 03-21-2013 |
20130127058 | LINER-FREE TUNGSTEN CONTACT - A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity. | 05-23-2013 |
20130149865 | METHOD AND STRUCTURE FOR DIFFERENTIAL SILICIDE AND RECESSED OR RAISED SOURCE/DRAIN TO IMPROVE FIELD EFFECT TRANSISTOR - A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc. | 06-13-2013 |
20130154098 | LINER-FREE TUNGSTEN CONTACT - An electrical structure comprises a dielectric layer present on a semiconductor substrate. A contact opening is present through the dielectric layer. A nickel-tungsten alloy silicide is formed over the semiconductor substrate within the contact opening. A tungsten-containing nucleation layer formed within the contact opening covers the nickel-tungsten alloy silicide and at least a portion of a sidewall of the contact opening. A tungsten contact is formed within the contact opening and separated from the nickel-tungsten alloy silicide and at least a portion of the sidewall by the tungsten-containing nucleation layer. | 06-20-2013 |
20130175606 | INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 07-11-2013 |
20130175626 | INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 07-11-2013 |
20130187171 | METHOD TO FORM SILICIDE CONTACT IN TRENCHES - A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region. | 07-25-2013 |
20130189839 | METHOD TO FORM SILICIDE CONTACT IN TRENCHES - A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region. | 07-25-2013 |
20130200443 | Interface Engineering to Optimize Metal-III-V Contacts - Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact. | 08-08-2013 |
20130207189 | INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 08-15-2013 |
20140274725 | CHIP MODE ISOLATION AND CROSS-TALK REDUCTION THROUGH BURIED METAL LAYERS AND THROUGH-VIAS - A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate. | 09-18-2014 |
20140306290 | Dual Silicide Process Compatible with Replacement-Metal-Gate - In one aspect, a method for fabricating an electronic device includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined therein. One or more p-FET/n-FET devices are formed in the active areas, each having a p-FET/n-FET gate stack and p-FET/n-FET source and drain regions. A self-aligned silicide is formed in each of the p-FET/n-FET source and drain regions, wherein the self-aligned silicide in each of the p-FET source and drain regions has a thickness T1 and the self-aligned silicide in each of the n-FET source and drain regions having a thickness T2, wherein T1 is less than T2. During a subsequent trench silicidation in the p-FET/n-FET source and drain regions, the trench silicide metal will diffuse through the thinner self-aligned silicide in the p-FET device(s) but not through the thicker self-aligned silicide in the n-FET device(s). | 10-16-2014 |
20140306291 | Dual Silicide Process Compatible with Replacement-Metal-Gate - In one aspect, a method for fabricating an electronic device includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined therein. One or more p-FET/n-FET devices are formed in the active areas, each having a p-FET/n-FET gate stack and p-FET/n-FET source and drain regions. A self-aligned silicide is formed in each of the p-FET/n-FET source and drain regions, wherein the self-aligned silicide in each of the p-FET source and drain regions has a thickness T1 and the self-aligned silicide in each of the n-FET source and drain regions having a thickness T2, wherein T1 is less than T2. During a subsequent trench silicidation in the p-FET/n-FET source and drain regions, the trench silicide metal will diffuse through the thinner self-aligned silicide in the p-FET device(s) but not through the thicker self-aligned silicide in the n-FET device(s). | 10-16-2014 |
20140353796 | Fin eFuse Formed by Trench Silicide Process - A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes an enhanced performance electrical fuse formed in a polysilicon fin using a trench silicide process. In one embodiment, at least one semiconductor fin is formed on a dielectric layer present on the surface of a semiconductor substrate. An isolation layer may be formed over the exposed portions of the dielectric layer and the at least one semiconductor fin. At least two contact vias may be formed through the isolation layer to expose the top surface of the semiconductor fin. A continuous silicide may be formed on and substantially below the exposed surfaces of the semiconductor fin extending laterally at least between the at least two contact vias to form an electronic fuse (eFuse). In another embodiment, the at least one semiconductor fin may be subjected to ion implantation to facilitate the formation of silicide. | 12-04-2014 |