Patent application number | Description | Published |
20130037953 | THROUGH SILICON VIA STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method for a through silicon via structure includes the following steps. First, a substrate is provided, and a through silicon hole is formed in the substrate. An outer plasma enhanced oxide layer is formed on the surface of the through silicon hole, and then a liner layer is formed on the surface of the outer plasma enhanced oxide layer. An inner plasma enhanced oxide layer is formed on the surface of the liner layer. Finally, a conductor is formed on the surface of the inner plasma enhanced oxide layer to completely fill the through silicon hole. | 02-14-2013 |
20130161796 | THROUGH SILICON VIA AND METHOD OF FORMING THE SAME - The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV. | 06-27-2013 |
20130270712 | Through silicon via structure and method of fabricating the same - A through silicon via structure and a method of fabricating the through silicon via structure are disclosed. After an interlayer dielectric is formed, a via hole is then formed to pass through the interlayer dielectric; thereafter, a dielectric liner is formed within the via hole and extends onto the interlayer dielectric; thereafter, the via hole is filled with a conductive material; and a chemical-mechanical polishing process is performed to planarize the conductive material, using the dielectric liner on the interlayer dielectric as a stop layer of the chemical-mechanical polishing process. | 10-17-2013 |
20130299949 | Through Silicon Via and Method of Forming the Same - The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface. | 11-14-2013 |
20130341799 | Through silicon via structure and method of fabricating the same - A method of fabricating a through silicon via (TSV) structure is provided, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the second dielectric layer covers a sidewall of the via hole. A conductive material layer is formed to fill the via hole and the second opening. The conductive material layer is planarized to form a TSV within the via hole. A TSV structure is also provided, in which, the second dielectric layer is disposed within the first opening and on the sidewall of the via hole. | 12-26-2013 |
20140057434 | THROUGH SILICON VIA PROCESS - A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer. | 02-27-2014 |
20140291801 | ANTI-FUSE STRUCTURE AND PROGRAMMING METHOD THEREOF - A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically. | 10-02-2014 |
20140367835 | Die Seal Ring and Method of Forming the Same - A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring. | 12-18-2014 |
20150041961 | Through silicon via structure - A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via. | 02-12-2015 |