Patent application number | Description | Published |
20080248623 | Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach - A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region. | 10-09-2008 |
20090212392 | Capacitor Pairs with Improved Mismatch Performance - A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two. | 08-27-2009 |
20100213575 | Profile Design for Lateral-Vertical Bipolar Junction Transistor - A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter. | 08-26-2010 |
20110193174 | Multiple Silicide Integration Structure and Method - A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices. | 08-11-2011 |
20110215420 | CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage. | 09-08-2011 |
20120018811 | FORMING BIPOLAR TRANSISTOR THROUGH FAST EPI-GROWTH ON POLYSILICON - Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well. | 01-26-2012 |
20140246751 | Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit includes a substrate having a first resistance, the substrate including an implant region, a buried oxide layer disposed over the substrate, an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than the first resistance, a silicon layer disposed over the buried oxide layer, and an interlevel dielectric disposed in a deep trench, the deep trench extending through the silicon layer, the buried oxide layer, and the interface layer over the implant region. In an embodiment, the deep trench extends through a polysilicon layer disposed over the silicon layer. | 09-04-2014 |
20150132918 | Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer. | 05-14-2015 |