Patent application number | Description | Published |
20100010142 | COMPOSITION OF POLYPROPYLENE RESIN HAVING LOW SHRINKAGE AND DIMENSIONAL STABILITY - The present invention relates to polypropylene-based composite resin composition for an automotive interior trim. The polypropylene-based composite resin composition herein has relatively high rigidity and surface impact and relatively low molding shrinkage and coefficient of linear expansion, thus having superior dimensional stability. | 01-14-2010 |
20120213918 | VERTICALLY ALIGNING A CARBON NANOTUBES ARRAY - The present invention provides a technique for vertically aligning a carbon nanotube array, which can improve vertical alignment at the bottom of the carbon nanotube array during growth of carbon nanotubes on a substrate. For this purpose, the present invention provides a method of vertically aligning a carbon nanotube array, the including: allowing carbon nanotubes to be grown on a substrate fed to a reactor and synthesized into a carbon nanotube array; and reducing the internal pressure of the reactor after (e.g., immediately after) synthesis of the carbon nanotube array to remove (e.g., instantly remove) a carbon source gas remaining in the reactor, thereby improving vertical alignment at the bottom of the carbon nanotube array. | 08-23-2012 |
20130252059 | BATTERY PACK CASE ASSEMBLY FOR ELECTRIC AND HYBRID VEHICLES USING A PLASTIC COMPOSITE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a battery pack case assembly for an electric or hybrid vehicle and a method for manufacturing the same. The battery pack case assembly includes a case body and a cover. The case body receives a battery pack, and the cover is coupled to the case body. The case body is formed of a plastic composite in which a long fiber or a blend of a long fiber and a continuous fiber is used as a reinforcing fiber in a plastic matrix. A separate reinforced member is bonded to both side bracket parts for coupling to a vehicle body, and is formed of a plastic composite in which a long fiber, a continuous, or a blend of a long fiber and a continuous fiber is used as the reinforcing fiber in the plastic matrix. | 09-26-2013 |
Patent application number | Description | Published |
20090073342 | Liquid crystal display device - A liquid crystal display device has a reinforced rigidity against external impacts. The liquid crystal display device includes a liquid crystal display panel and a backlight assembly; and a bottom chassis disposed to receive the liquid crystal display panel and the backlight assembly, the bottom chassis having a projection projected from an inner surface of the bottom chassis towards the liquid crystal display panel and the backlight assembly. | 03-19-2009 |
20100082708 | System and Method for Management of Performance Fault Using Statistical Analysis - A system includes: at least one managed resource having an agent for collecting and transmitting performance information; an integrated management server for receiving the information and managing it in an integrated manner; a statistical information generating module for extracting previously set performance items and automatically generating statistical information for each performance item; and a fault management server for receiving the information from the integrated management server in real time, performing statistical analysis on current performance information, comparing the analysis results with the information generated by the statistical information generating module to determine whether a fault is likely to occur, generating a fault event according to the determination result, and transmitting the fault event to the integrated management server. | 04-01-2010 |
20100088552 | Method for Obstruction and Capacity Information Unification Monitoring in Unification Management System Environment and System for Thereof - Provided are a method and system for integrated monitoring of fault and performance information in an integrated management system environment including an integrated management server that interworks with a managed server having a built-in agent for the sake of integrated management of a variety of management information. The method includes the steps of: collecting, at the agent, in real time, fault information data of the managed server using queues; periodically collecting, at the agent, performance information data of the managed server using a function-specific remote function module (REM); converting, at the agent, the fault and performance information data collected from the managed server into a format that the integrated management server can recognize and transferring it; receiving, at the integrated management server, the fault information data from the agent, and generating and transferring an event message to a corresponding administrator terminal; and receiving, at the integrated management server, the performance information data from the agent and storing it in a previously prepared database (DB). Therefore, even when a user docs not directly access a managed server, fault and performance information data is transferred in real time to the corresponding administrator so that loss due to faults can be minimized. | 04-08-2010 |
20100145950 | Realtime Unification Management Information Data Conversion and Monitoring Apparatus and Method for Thereof - Provided are an apparatus and method for converting and monitoring management information data in an integrated manner and in real time. More particularly, the present invention relates to an apparatus and method for converting and monitoring management information data in an integrated manner and in real time which are capable of reducing the number of processes and stably operating an IT infrastructure through integrated management by flexibly collecting and converting management information data having a variety of formats and transmitting it to a destination integrated management solution when existing point-specific management solutions are managed in an integrated manner using an integrated management solution. | 06-10-2010 |
Patent application number | Description | Published |
20090113178 | Microprocessor based on event-processing instruction set and event-processing method using the same - Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated. | 04-30-2009 |
20100135430 | DATA TRANSMITTING DEVICE, DATA RECEIVING DEVICE, DATA TRANSMITTING SYSTEM, AND DATA TRANSMITTING METHOD - Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method. | 06-03-2010 |
20120166170 | DELAY CIRCUIT, AND DEVICE AND METHOD FOR SIMULATING ASYNCHRONOUS CIRCUIT IN FPGA USING DELAY CIRCUIT - Disclosed herein is an apparatus for simulating an asynchronous circuit in an FPGA. The apparatus includes a plurality of function execution units, a plurality of delay circuits, and a control unit. The function execution units are set for respective unit functions included in the asynchronous circuit, and are configured to perform the unit functions. The delay circuits are provided for the respective function execution units using a look-up table in the FPGA, and are configured to output delayed input signals by delaying input signals by respective preset delay times. The control unit transmits the input signals to the delay circuits and the function execution units, and receives the delayed input signals from the respective delay circuits. | 06-28-2012 |
20130259166 | DATA TRANSMISSION APPARATUS, DATA RECEPTION APPARATUS, AND DATA TRANSMISSION METHOD - Disclosed herein are a data transmission apparatus, a data reception apparatus, and a data transmission method. The data transmission apparatus, the data reception apparatus, and the data transmission method are capable of simplifying the circuit structure of a decoder because an assumption of the time related to a request signal and a data signal is not necessary and an additional logic for generating a clock signal for the decoder is not necessary by using a Finite State Machine (FSM) logic without storing a state via a delay device. | 10-03-2013 |
20130326454 | APPARATUS AND METHOD FOR REDUCING PEAK POWER USING ASYNCHRONOUS CIRCUIT DESIGN TECHNOLOGY - Disclosed herein are an apparatus and method for reducing peak power using an asynchronous circuit design technology. The apparatus includes a combinational circuit unit and an asynchronous control circuit unit. The combinational circuit unit divides a combinational circuit into a plurality of partial circuits based on the depth of input and output. The asynchronous control circuit unit controls the combinational circuit so that the switching operations of the partial circuits are performed in an asynchronous manner according to temporal order and so that a switching operation is not performed in other partial circuits when a switching operation is performed in a partial circuit. | 12-05-2013 |