Patent application number | Description | Published |
20080230814 | Methods for fabricating a semiconductor device - A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the first, second, and third gate stacks, the spacer overlying a portion of the silicon-containing substrate in the first, second, and third regions, respectively. A source/drain region is formed in a portion of the silicon-containing substrate in the first, second, and third regions, with the source/drain region adjacent to the first, second, and third gate stacks, respectively. The first, second, and third gate stacks have first, second, and third gate dielectric layers of various thicknesses and at least one thereof with a relatively thin thickness is treated by NH | 09-25-2008 |
20080293204 | Shallow junction formation and high dopant activation rate of MOS devices - A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer. | 11-27-2008 |
20090047799 | GATE OXIDE LEAKAGE REDUCTION - A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation process, subjecting the gate oxide layer to a first anneal process after the first nitridation process, subjecting the gate oxide layer to a second nitridation process after the first anneal process, subjecting the gate oxide layer to a second anneal process after the second nitridation process, and forming a gate electrode over the gate oxide. | 02-19-2009 |
20100048011 | METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process. | 02-25-2010 |
20100052076 | METHOD OF FABRICATING HIGH-K POLY GATE DEVICE - The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer. | 03-04-2010 |
20100068875 | DOUBLE TREATMENT ON HARD MASK FOR GATE N/P PATTERNING - The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region, forming first and second gate stacks over the first and second regions, respectively, the first and second gate stacks each including a dummy gate electrode, removing the dummy gate electrodes from the first and second gate stacks, respectively, thereby forming trenches, forming a metal layer to partially fill the trenches, forming an oxide layer over the metal layer filling a remaining portion of the trenches, applying a first treatment to the oxide layer, forming a patterned photoresist layer on the oxide layer overlying the first region, applying a second treatment to the oxide layer overlying the second region, etching the oxide layer overlying the second region, etching the first metal layer overlying the second region, removing the patterned photoresist layer, and removing the oxide layer overlying the first region. | 03-18-2010 |
20100081262 | METHOD FOR FORMING METAL GATES IN A GATE LAST PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP). | 04-01-2010 |
20100112811 | METHOD FOR PATTERNING A METAL GATE - The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer. | 05-06-2010 |
20100124818 | FABRICATING HIGH-K/METAL GATE DEVICES IN A GATE LAST PROCESS - The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches. | 05-20-2010 |
20110117734 | Method of Fabricating High-K Poly Gate Device - The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer. | 05-19-2011 |
20110316079 | Shallow Junction Formation and High Dopant Activation Rate of MOS Devices - A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer. | 12-29-2011 |
20130130488 | Method of Patterning a Metal Gate of Semiconductor Device - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process. | 05-23-2013 |