Patent application number | Description | Published |
20130128676 | MEMORY DEVICE WITH AREA EFFICIENT POWER GATING CIRCUITRY - A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode. | 05-23-2013 |
20130343139 | ADJUSTING ACCESS TIMES TO MEMORY CELLS BASED ON CHARACTERIZED WORD-LINE DELAY AND GATE DELAY - A memory tracking circuit activates a reset signal that resets a word-line pulse generator to switch the memory from an access state to a recess state. Activation is based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. If the memory is in a fast PVT condition such that the gate delay is of less duration than, or substantially equal to, the propagation delay, then a slow-down circuit delays activation of the reset signal to allow sufficient access margin. The delay in the latter case is less than that in the former case. If the memory is in a slow PVT condition such that the gate delay is longer than the propagation delay, then the slow-down circuit does not delay activation of the reset signal to prevent excess access margin. | 12-26-2013 |
20140071775 | ADJUSTING BIT-LINE DISCHARGE TIME IN MEMORY ARRAYS BASED ON CHARACTERIZED WORD-LINE DELAY AND GATE DELAY - A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions. | 03-13-2014 |
20150138863 | INTERLEAVED WRITE ASSIST FOR HIERARCHICAL BITLINE SRAM ARCHITECTURES - An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines. | 05-21-2015 |
20150138864 | MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES - Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines. | 05-21-2015 |
20150138876 | GLOBAL BITLINE WRITE ASSIST FOR SRAM ARCHITECTURES - An SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the memory cell segments via the local bitlines for writing to the memory cells. The SRAM device further includes a global input/output module operable to hold the global bitline at logical zero, to toggle the global bitline to logical one when data is to be written, to select one of the segments of memory cells for writing after the global bitline has been toggled, and to toggle the global bitline to logical zero when data is written to the selected memory cell segment to provide a negative boost voltage to the local bitline of the selected memory cell segment. | 05-21-2015 |
20150255148 | BIT LINE WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARCHITECTURES - SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state. | 09-10-2015 |
20150302918 | WORD LINE DECODERS FOR DUAL RAIL STATIC RANDOM ACCESS MEMORIES - Word line decoders for dual rail SRAM devices are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array. A row decode-driver coupled to the word line toggles the word line between logic levels of a memory cell supply based on select signals that toggle between logic levels of a peripheral supply. The row decoder-driver toggles the word line without utilizing level shifters along the word line access path. | 10-22-2015 |
Patent application number | Description | Published |
20120307844 | Synchronization of Shared Identifiers Across Servers in an IMS Network - Methods and apparatuses, including computer program products, are described for synchronization of shared initial filter criteria in an IP Multimedia Subsystem (IMS) network. A first computing device in the IMS network transmits a registration request to a second computing device in the IMS network. The first computing device receives a response to the registration request from the second computing device, including an identifier associated with a shared initial filter criteria set stored at the first computing device. The first computing device determines whether the shared initial filter criteria set corresponding to the identifier is stored at the first computing device and transmits a retrieval request to the second computing device if the shared initial filter criteria set corresponding to the identifier is not stored. The first computing device receives the shared initial filter criteria set from the second computing device, and stores the shared initial filter criteria set. | 12-06-2012 |
20130085881 | Mobile and Web Commerce Platform for delivery of Business Information and Service Status Management. - Described in this invention are the methods and system platform for businesses and organizations to publish and communicate to consumers business information and real-time dynamic service information in a central and intuitive place on mobile devices and computers that is based on a generic, configurable, extensible, and vendor-independent mobile-commerce and electronic-commerce cloud based Software as a Service solution. The consumer and service providers use mobile device application client software and computer-based web browser client application software that are part of the platform solution to access and manage the information stored on the platform. The platforms allow service providers to perform functions such as: publish business information, real-time dynamic service status information, manage loyalty programs, manage customer marketing programs, and take online reservations. The platform allows consumers to perform functions such as: search for the business or service near a geo-location, obtain for the above-mentioned information, and subscribe for the programs. | 04-04-2013 |
20150319239 | SYNCHRONIZATION OF SHARED IDENTIFIERS ACROSS SERVERS IN AN IMS NETWORK - Methods and apparatuses, including computer program products, are described for synchronization of shared initial filter criteria in an IP Multimedia Subsystem (IMS) network. A first computing device in the IMS network transmits a registration request to a second computing device in the IMS network. The first computing device receives a response to the registration request from the second computing device, including an identifier associated with a shared initial filter criteria set stored at the first computing device. The first computing device determines whether the shared initial filter criteria set corresponding to the identifier is stored at the first computing device and transmits a retrieval request to the second computing device if the shared initial filter criteria set corresponding to the identifier is not stored. The first computing device receives the shared initial filter criteria set from the second computing device, and stores the shared initial filter criteria set. | 11-05-2015 |