Patent application number | Description | Published |
20090182964 | DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If the format control field is enabled, a frame address of a large block of data in main storage is obtained from the translation table entry. The large block of data is a block of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a desired block of data within the large block of data in main storage. The desired large block of data addressed by the translated address is then accessed. | 07-16-2009 |
20090182971 | DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field. | 07-16-2009 |
20090182972 | DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 07-16-2009 |
20090187728 | DYNAMIC ADDRESS TRANSLATION WITH CHANGE RECORDING OVERRIDE - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. A segment table entry obtained from a segment table contains a format control field. If the format control field is enabled, a segment-frame absolute address of a large block of data in main storage is obtained from the segment table entry. Each 4K byte block of data within the large block has an associated storage key. Store operations associated with the virtual address are performed to the desired block of data. If the change recording override field is disabled, the change bit of the storage key associated with the desired 4K byte block is set to 1. An indication is then provided that the desired 4K byte block has been modified. | 07-23-2009 |
20090187732 | DYNAMIC ADDRESS TRANSLATION WITH DAT PROTECTION - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained. Based on the obtained initial origin address, a segment table entry is obtained which contains a format control and DAT protection fields. If the format control field is enabled, obtaining from the translation table entry a segment-frame absolute address of a large block of data in main storage. The segment-frame absolute address is combined with a page index portion and a byte index portion of the virtual address to form a translated address of the desired block of data. If the DAT protection field is not enabled, fetches and stores are permitted to the desired block of data addressed by the translated virtual address. | 07-23-2009 |
20090198980 | FACILITATING PROCESSING IN A COMPUTING ENVIRONMENT USING AN EXTENDED DRAIN INSTRUCTION - An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. | 08-06-2009 |
20090204763 | SYSTEM AND METHOD FOR AVOIDING DEADLOCKS WHEN PERFORMING STORAGE UPDATES IN A MULTI-PROCESSOR ENVIRONMENT - A system and method for avoiding deadlocks when performing storage updates in a multi-processor environment. The system includes a processor having a local cache, a store queue having a temporary buffer with capability to reject exclusive cross-interrogates (XI) while an interrogated cache line is owned exclusive and is to be stored, and a mechanism for performing a method. The method includes setting the processor into a slow mode. A current instruction that includes a data store having one or more target lines is received. The current instruction is executed, with the executing including storing results associated with the data store into the temporary buffer. The store queue is prevented from rejecting an exclusive XI corresponding to the target lines of the current instruction. Each target line is acquired with a status of exclusive ownership, and the contents from the temporary buffer are written to each target line after instruction completion. | 08-13-2009 |
20090210661 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AN IMPLICIT PREDICTED RETURN FROM A PREDICTED SUBROUTINE - A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction. | 08-20-2009 |
20090210662 | MICROPROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR DIRECT PAGE PREFETCH IN MILLICODE CAPABLE COMPUTER SYSTEM - A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided. | 08-20-2009 |
20090216951 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR HANDLING SHARED CACHE LINES IN A MULTI-PROCESSOR ENVIRONMENT - A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject that is followed by an instruction completion, and reset on an exclusive XI acknowledgement. If the XI reject counter reaches a preset threshold value, the processor's pipeline is drained by blocking instruction issue and prefetching attempts, creating a window for an exclusive XI from another processor to be honored, after which normal instruction processing is resumed. Configuring the preset threshold value as a programmable value allows for fine-tuning of system performance. | 08-27-2009 |
20090216963 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A SHARED MEMORY TRANSLATION FACILITY - A system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined if the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations. In response to determining that the memory address refers to the SMO, it is determined if the configuration has access to the SMO. In response to determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the plurality of configurations is allowed. | 08-27-2009 |
20090216994 | PROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR FAST SELECTIVE INVALIDATION OF TRANSLATION LOOKASIDE BUFFER - A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided. | 08-27-2009 |
20090217009 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING STORAGE ELEMENTS - A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value. | 08-27-2009 |
20090217264 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING FILTERING OF GUEST2 QUIESCE REQUESTS - A method, system and computer program product for providing filtering of level two guest (G2) quiesce requests. The method includes receiving a G2 quiesce interruption request at a processor currently or previously executing a G2 running under a level two hypervisor in a logical partition. The G2 includes a current zone and G2 virtual machine (VM) identifier. The quiesce interruption request specifies an initiating zone and an initiating G2 VM identifier. It is determined if the G2 quiesce interruption request can be filtered by the processor. The determining is responsive to the current G2 VM identifier, the current zone, the initiating zone and the initiating G2 VM identifier. The G2 quiesce interruption request is filtered at the processor in response to determining that the G2 quiesce interruption request can be filtered. Thus, filtering between G2 virtual machines running in the logical partition is provided. | 08-27-2009 |
20090240929 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR REDUCED OVERHEAD ADDRESS MODE CHANGE MANAGEMENT IN A PIPELINED, RECYLING MICROPROCESSOR - A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode. | 09-24-2009 |
20100287358 | Branch Prediction Path Instruction - A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address. | 11-11-2010 |
20110202748 | LOAD PAIR DISJOINT FACILITY AND INSTRUCTION THEREFORE - A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers. | 08-18-2011 |
20110320774 | OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE - A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping. | 12-29-2011 |
20120036338 | FACILITATING PROCESSING IN A COMPUTING ENVIRONMENT USING AN EXTENDED DRAIN INSTRUCTION - An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. | 02-09-2012 |
20120137106 | Dynamic Address Translation With Translation Table Entry Format Control for Identifying Format of the Translation Table Entry - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 05-31-2012 |
20120144153 | Dynamic Address Translation With Change Record Override - A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether the change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation. | 06-07-2012 |
20130091343 | OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE - Data operand fetching control includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The data operand fetching control also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control. Each memory access control specifies a manner of handling data fetching operations. The data operand fetching control further includes performing a memory access operation for the selected instruction based upon the mapping. | 04-11-2013 |
20130117546 | Load Pair Disjoint Facility and Instruction Therefore - A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers. | 05-09-2013 |
20130311726 | SHARED MEMORY TRANSLATION FACILITY - Aspects include a system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined whether the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations managed in different zones of memory. Based on determining that the memory address refers to the SMO, it is determined whether the configuration has access to the SMO. Based on determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the configuration and the plurality of configurations is allowed. | 11-21-2013 |
20140115295 | DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION IN AN EMULATED ENVIRONMENT - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled. | 04-24-2014 |
20140181463 | Dynamic Address Translation with Translation Table Entry Format Control for Identifying Format of the Translation Table Entry - An enhanced dynamic address translation facility is provided. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 06-26-2014 |
20140188452 | Emulation of a Dynamic Address Translation With Change Record Override on a Machine of Another Architecture - A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation. | 07-03-2014 |