Patent application number | Description | Published |
20090323768 | SPREAD SPECTRUM CLOCK SIGNAL GENERATOR - A spread spectrum clock signal generator for spreading an input clock signal into an output clock signal includes a clock signal delay chain for delaying the input clock signal into a delay clock signal group having a plurality of delay clock signals, a modulation controller for outputting a counter clock signal control signal, a clock signal selection circuit for selecting, from the delay clock signal group, a modulation clock signal group having a plurality of modulation clock signals, a programmable counter for generating a counting value according to a counter clock signal, and a clock signal output unit for combining the modulation clock signals into the output clock signal according to the counting value, and further generating the counter clock signal, outputted to the programmable counter, according to the counter clock signal control signal. | 12-31-2009 |
20100110115 | Frame Rate Control Method and Display Device Using the Same - A frame rate control (FRC) method is provided for driving a number of pixels according to a number of pixels data. The pixels include a number of first color sub-pixels. In this method, the dithering process is performed to the pixels data in two frames according to two basic matrixes respectively. In one of the two frames, the numbers of the first color sub-pixels, driven by the positive pixel voltages and the negative pixel voltages and to which the dithering process has been performed, are the same in substantiality. Further, in the other of the two frames, the numbers of the first color sub-pixels, driven by the positive pixel voltages and the negative pixel voltages and to which the dithering process has been performed, are also the same in substantiality. | 05-06-2010 |
20120169641 | TOUCH SENSING APPARATUS - A touch sensing apparatus includes a logic control module, a plurality of storage capacitors, at least one decoding control module, and at least one differential amplifier. The logic control module generates a plurality of control signals having different control timings, wherein the control signals comprise a decoding control signal. The decoding control module is coupled with the logic control module and the storage capacitors and decodes according to a decoding control timing of a decoding control signal and outputs a first sensing voltage and a second sensing voltage of the storage capacitors. The differential amplifier is coupled with the decoding control module and calculates a voltage variance between the first sensing voltage and the second sensing voltage to output an amplified analog data. | 07-05-2012 |
20120169654 | TOUCH SENSING APPARATUS - A touch sensing apparatus includes a plurality of pins, a logic control module, and at least one driving/sensing module. The driving/sensing control module is coupled with the pins and the logic control module. The driving/sensing control module controls the pins to execute a driving function according to a driving control signal at high voltage level and output a high voltage to a conductive thin film sensor. The driving/sensing control module includes an isolating switch, a high voltage device, and a medium/low voltage device, wherein the isolating switch is coupled with the high voltage device and the medium/low voltage device. The driving/sensing control module activates the isolating switch according to a isolating control signal at high voltage level to isolate the medium/low voltage device from the high voltage device for avoiding the high voltage from entering into the medium/low device that results in the damage of the medium/low voltage device. | 07-05-2012 |
20120169657 | TOUCH SENSING APPARATUS - The present invention provides a touch sensing apparatus including a plurality of pins, a logic control module, and at least one driving/sensing control module. The logic control module generates a plurality of control signals having different control timings. Each driving/sensing control module is coupled with the logic control module and the pins, wherein the driving/sensing control module receives a first control signal of the control signals from the logic control module and controls the pins to execute a plurality of pin functions according to a first control timing of the first control signal, so that the pins simultaneously sense a plurality of analog data from a conductive thin film sensor. | 07-05-2012 |
20120169661 | TOUCH SENSING APPARATUS - A touch sensing apparatus is disclosed. The touch sensing apparatus includes a logic control module, at least one storage control module, and at least one decoding control module. The logic control module is used to generate a plurality of control signals having different control timings. The plurality of control signals includes a storage control signal and a decoding control signal. Each storage control module includes a plurality of storage capacitors, and respectively stores each of sensed voltages in different storage capacitors at different times according to a storage control timing of the storage control signal. The sensed voltages are analog data sensed from scan lines of an ITO sensor. The decoding control module is used to decode the sensed voltages stored in the storage capacitors according to a decoding control timing of the decoding control signal to output the decoded analog data. | 07-05-2012 |
20120169662 | TOUCH SENSING APPARATUS - A touch sensing apparatus is disclosed. The touch sensing apparatus includes a logic control module, at least one storage control module, and at least one decoding control module. The logic control module is used to generate a plurality of control signals having different control timings. The plurality of control signals includes a storage control signal and a decoding control signal. Each storage control module includes a plurality of storage capacitors, and respectively stores each of sensed voltages in different storage capacitors at different times according to a storage control timing of the storage control signal. The sensed voltages are analog data sensed from scan lines of an ITO sensor. The decoding control module performs analog adding process to the sensed voltages stored in the storage capacitors according to a decoding control timing of the decoding control signal to output decoded analog data with high signal-to-noise ratio (SNR). | 07-05-2012 |
20120206389 | TOUCH SENSING APPARATUS - A touch sensing apparatus includes a plurality of pins, a logic control module, and at least one amplifier module. The logic control module generates a plurality of control signals having different control timings, wherein the control signals include an amplifying control signal and a compensating control signal. Each amplifying module includes an amplifying unit and an automatic compensating unit. The amplifying unit includes a positive input end and a negative input end, wherein the amplifying unit determines, according to the amplifying control signal, a difference between a first sensing voltage and a second sensing voltage respectively received by the positive input end and the negative input end and amplifies the difference to output an analog data. The automatic compensating unit records, according to the compensating control signal, a digital compensation value corresponding to one of the pins and outputs the digital compensation value according to the compensating control signal. | 08-16-2012 |
20120206404 | TOUCH SENSING APPARATUS - A touch sensing apparatus includes a logic control module and at least one input control module. The logic control module generates a plurality of control signals having different control timings, wherein the control signals include an input control signal. The input control module is coupled with the logic control module, wherein each input control module includes a positive input switch and a negative input switch. The input control module controls, according to the input control signal, the positive input switch and the negative input switch to be deactivated or activated to control an input mode of a first sensing voltage and a second sensing voltage, which are analog data respectively sensed through a first sensing line and a second sensing line of a conductive thin film sensor, wherein the first sensing line and the second sensing line are sensing lines of adjacent channels. | 08-16-2012 |
20120256855 | DRIVING AND SENSING METHOD FOR TOUCH-SENSING INPUT DEVICE, AND MODULE USING THE SAME - The disclosure provides a driving and sensing method for a touch-sensing input device including a touch-sensing panel module and a liquid crystal display panel module. The touch-sensing panel module includes a touch-sensing panel and a control device, wherein the touch-sensing panel includes a plurality of X-directional lines and Y-directional lines arranged intersecting one another. The method includes steps of generating a spread spectrum clock signal using the control device; generating a driving signal and a sensing signal based on the spread spectrum clock signal; outputting the driving signal to one of the X-directional lines or one of the Y-directional lines; receiving voltages on the corresponding Y-directional line or X-directional line in response to the sensing signal and converting the same to a digital signal; and determining a touch status of the touch-sensing panel based on the digital signal. | 10-11-2012 |
20120262395 | METHOD OF UPDATING BASELINE OUTPUT VALUES OF TOUCH PANEL - An updating method for baseline output values of a touch-sensing panel is disclosed. The touch-sensing panel includes a plurality of X-directional lines and a plurality of Y-directional lines. The X-directional lines and Y-directional lines are arranged intersecting one another so as to form a sensing grid with a plurality of sensing nodes. The method includes the following steps: performing a first scan when the touch-sensing panel is not touched so as to obtain a plurality of first baseline output values; performing a second scan after the touch-sensing panel is touched so as to obtain plurality of touch output values; and updating the baseline output values on the sensing nodes based on a threshold, the first baseline output values and the touch output values. | 10-18-2012 |
20130009885 | TOUCH CONTROL SENSING APPARATUS AND METHOD THEREOF - A touch control sensing apparatus comprises a logic control module configured to generate a plurality of control signals, a driving sensing control module having a parallel sensing control unit coupled to the logic control module, a signal comparing module having at least one amplifier coupled to the logic control module, a parallel to serial control module coupled to the logic control module, and an analog digital convertor coupled between the logic control module and the parallel to serial control module. | 01-10-2013 |
20130027317 | METHOD FOR PROVIDING DIGITAL SENSING DATA FOR TOUCH PANEL APPARATUS - A method for providing digital sensing data for a touch panel apparatus comprises the steps of: collecting a stream of digital sensing data from a plurality of operational amplifiers of a touch panel apparatus; generating a first revised digital datum to replace a first digital datum by summing the first digital datum and a digital datum following the first digital datum; generating a second revised digital datum to replace a second digital datum by summing the first revised digital datum and the second digital datum, wherein the second digital datum follows the first revised digital datum; and continuing to generate revised digital sensing data until a last revised digital datum is generated. | 01-31-2013 |
20130044064 | TOUCH CONTROL SENSING APPARATUS AND METHOD THEREOF - A touch control sensing apparatus comprises a logic control module configured to generate a plurality of control signals, a driving sensing control module having a parallel sensing control unit coupled to the logic control module, a signal comparing module having at least one amplifier and a signal selecting unit coupled to the logic control module, and a parallel to serial control module coupled to the logic control module and an analog-digital converter, wherein the analog-digital converter is coupled between the logic control module and the parallel to serial control module. | 02-21-2013 |
Patent application number | Description | Published |
20110220973 | JUNCTION-FIELD-EFFECT-TRANSISTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions. | 09-15-2011 |
20110291187 | Double Diffused Drain Metal-Oxide-Semiconductor Devices with Floating Poly Thereon and Methods of Manufacturing The Same - A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion. | 12-01-2011 |
20120104492 | LOW ON-RESISTANCE RESURF MOS TRANSISTOR - The present invention relates to a low on-resistance RESURF MOS transistor, comprising: a drift region; two isolation regions formed on the drift region; a first-doping-type layer disposed between the two isolation regions; and a second-doping-type layer disposed below the first-doping-type layer. | 05-03-2012 |
20120241900 | SELF DETECTION DEVICE FOR HIGH VOLTAGE ESD PROTECTION - An electrostatic discharge (ESD) protected device may include a substrate, an N-type well region disposed corresponding to a first portion of the substrate and having two N+ segments disposed at a surface thereof, an a P-type well region disposed proximate to a second portion of the substrate and having a P+ segment and an N+ segment. The two N+ segments may be spaced apart from each other and each may each be associated with an anode of the device. The N+ segment may be associated with a cathode of the device. A contact may be positioned in a space between the two N+ segments and connected to the P+ segment. The contact may form a parasitic capacitance that, in connection with a parasitic resistance formed in association with the N+ segment, provides self detection for high voltage ESD protection. | 09-27-2012 |
20120248574 | Semiconductor Structure and Manufacturing Method and Operating Method for the Same - A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type. | 10-04-2012 |
20120286362 | Semiconductor Structure and Circuit with Embedded Schottky Diode - A semiconductor structure is proposed. A third well is formed between a first well and a second well. A first doped region and a second doped region are formed in a surface of the third well. A third doped region is formed between the first doped region and the second doped region. A fourth doped region is formed in a surface of the first well. A fifth doped region is formed in a surface of the second well. A first base region and a second base region are respectively formed in surfaces of the first well and the second well. A first Schottky barrier is overlaid on a part of the first base region and the first doped region. A second Schottky barrier is overlaid on a part of the second base region and the second doped region. | 11-15-2012 |
20120292689 | Semiconductor Structure and Method for Operating the Same - A semiconductor structure and a method for operating the same are provided. The semiconductor structure includes a substrate, a first doped region, a second doped region, a third doped region, a first trench structure and a second gate structure. The first doped region is in the substrate. The first doped region has a first conductivity type. The second doped region is in the first doped region. The second doped region has a second conductivity type opposite to the first conductivity type. The third doped region having the first conductivity type is in the second doped region. The first trench structure has a first gate structure. The first gate structure and the second gate structure are respectively on different sides of the second doped region. | 11-22-2012 |
20120326261 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a well region, a dielectric structure, a first doped layer, a second doped layer and a first doped region. The dielectric structure is on the well region. The dielectric structure has a first dielectric sidewall and a second dielectric sidewall opposite to each other. The dielectric structure includes a first dielectric portion and a second dielectric portion, between the first dielectric sidewall and the second dielectric sidewall. The first doped layer is on the well region between the first dielectric portion and the second dielectric portion. The second doped layer is on the first doped layer. The first doped region is in the well region on the first dielectric sidewall. | 12-27-2012 |
20130015888 | SEMICONDUCTOR DEVICE, START-UP CIRCUIT, OPERATING METHOD FOR THE SAMEAANM Chan; Wing-ChorAACI Hsinchu CityAACO TWAAGP Chan; Wing-Chor Hsinchu City TWAANM Hu; Chih-MinAACI Kaohsiung CityAACO TWAAGP Hu; Chih-Min Kaohsiung City TWAANM Chen; Li-FanAACI Hsinchu CityAACO TWAAGP Chen; Li-Fan Hsinchu City TW - A semiconductor device, a start-up circuit, and an operating method for the same are provided. The start-up circuit comprises a semiconductor unit, a first circuit, a second circuit, a voltage input terminal and a voltage output terminal. The first circuit is constituted by one diode or a plurality of diodes electrically connected to each other in series. The second circuit is constituted by one diode or a plurality of diodes electrically connected to each other in series. The semiconductor unit is coupled to a first node between the first circuit and the second circuit. The voltage input terminal is coupled to the semiconductor unit. The voltage output terminal is coupled to a second node between the semiconductor unit and the first circuit. | 01-17-2013 |
20130049067 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME AND ESD CIRCUIT - A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region. | 02-28-2013 |
20130056824 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device and a manufacturing method for the same are provided. The semiconductor device comprises a first doped region, a second doped region, a dielectric structure and a gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity and is adjacent to the first doped region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doped region. The gate structure is on a part of the first doped region or second doped region adjacent to the first dielectric portion. | 03-07-2013 |
20130099293 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first doped region and a semiconductor region. The first doped region has a first type conductivity. The semiconductor region is in the first doped region. A source electrode and a drain electrode are respectively electrically connected to parts of the first doped region on opposite sides of the semiconductor region. | 04-25-2013 |
20130109139 | JUNCTION-FIELD-EFFECT-TRANSISTOR DEVICES AND METHODS OF MANUFACTURING THE SAME | 05-02-2013 |
20130214354 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first semiconductor region, a second semiconductor region, a dielectric structure and a gate electrode layer. The first semiconductor region has a first type conductivity. The second semiconductor region has a second type conductivity opposite to the first type conductivity. The first semiconductor region is adjoined to the second semiconductor region. The dielectric structure is on the first semiconductor region and the second semiconductor region. The gate electrode layer is on the dielectric structure. | 08-22-2013 |
20130249007 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer. | 09-26-2013 |
20130277805 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions. | 10-24-2013 |
20130328170 | SEMICONDUCTOR ELEMENT, MANUFACTURING METHOD THEREOF AND OPERATING METHOD THEREOF - A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well. | 12-12-2013 |
20140061790 | SPLIT-GATE LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - A semiconductor device includes a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure. | 03-06-2014 |
20140062578 | SEMICONDUCTOR STRUCTURE HAVING AN ACTIVE DEVICE AND METHOD FOR MANUFACTURING AND MANIPULATING THE SAME - A semiconductor structure comprising a substrate, an active device, a field oxide layer and a poly-silicon resistor is disclosed. The active device is formed in a surface area of the substrate. The active device has a first doped area, a second doped area and a third doped area. The second doped area is disposed on the first doped area. The first doped area is between the second and the third doped areas. The first doped area has a first type conductivity. The third doped area has a second type conductivity. The first and the second type conductivities are different. The field oxide layer is disposed on a part of the third doped area. The poly-silicon resistor is disposed on the field oxide layer and is electrically connected to the third doped area. | 03-06-2014 |
20140070281 | HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel. | 03-13-2014 |
20140106532 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME AND ESD CIRCUIT - A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region. | 04-17-2014 |
20140152349 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF AND OPERATING METHOD THEREOF - A semiconductor device, a manufacturing method thereof and an operating method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, a first heavily doping region, a second heavily doping region, a third heavily doping region, and an electrode layer. The first and the second wells are disposed on the substrate. The first and the third heavily doping regions, which are separated from each other, are disposed in the first well, and the second heavily doping region is disposed in the second well. The electrode layer is disposed on the first well. Each of the second well, the first heavily doping region, and the second heavily doping region has a first type doping. Each of the substrate, the first well, and the third heavily doping region has a second type doping, which is complementary to the first type doping. | 06-05-2014 |
20140159110 | SEMICONDUCTOR DEVICE AND OPERATING METHOD FOR THE SAME - A semiconductor device and an operating method for the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a first gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity. The first gate structure is on the second doped region. The third doped region and the fourth doped region are in the second doped region and the first doped region on opposing sides of the first gate structure respectively. | 06-12-2014 |
20140197466 | N-CHANNEL METAL-OXIDE FIELD EFFECT TRANSISTOR WITH EMBEDDED HIGH VOLTAGE JUNCTION GATE FIELD-EFFECT TRANSISTOR - A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET may include, according to a first example embodiment, a substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and first and second N+ doped regions disposed adjacent to the N-type well and on opposing sides of the P-type well region. The P-type well region may comprise a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure. | 07-17-2014 |
20140232513 | METHODS FOR MANUFACTURING AND MANIPULATING SEMICONDUCTOR STRUCTURE HAVING ACTIVE DEVICE - A semiconductor structure comprising a substrate, an active device, a field oxide layer and a poly-silicon resistor is disclosed. The active device is formed in a surface area of the substrate. The active device has a first doped area, a second doped area and a third doped area. The second doped area is disposed on the first doped area. The first doped area is between the second and the third doped areas. The first doped area has a first type conductivity. The third doped area has a second type conductivity. The first and the second type conductivities are different. The field oxide layer is disposed on a part of the third doped area. The poly-silicon resistor is disposed on the field oxide layer and is electrically connected to the third doped area. | 08-21-2014 |
20140253224 | SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD AND OPERATING METHOD OF THE SAME - A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping. | 09-11-2014 |
20140264581 | LOW ON RESISTANCE SEMICONDUCTOR DEVICE - A semiconductor device is provided having a dual dielectric layer structure defined by a thin dielectric layer adjacent to a thick dielectric layer. More particularly, a high voltage metal oxide semiconductor transistor having a dual gate oxide layer structure comprising a thin gate oxide layer adjacent to a thick oxide/thin oxide layer may be provided. Such structures may be used in extended drain metal oxide semiconductor field effect transmitters, laterally diffused metal oxide field effect transistors, or any high voltage metal oxide semiconductor transistor. Methods of fabricating an extended drain metal oxide semiconductor transistor device are also provided. | 09-18-2014 |
20140266407 | BIPOLAR JUNCTION TRANSISTOR AND OPERATING AND MANUFACTURING METHOD FOR THE SAME - A bipolar junction transistor and an operating method and a manufacturing method for the same are provided. The bipolar junction transistor comprises a first doped region, a second doped region and a third doped region. The first doped region has a first type conductivity. The second doped region comprises well regions formed in the first doped region, having a second type conductivity opposite to the first type conductivity, and separated from each other by the first doped region. The third doped region has the first type conductivity. The third doped region is formed in the well regions or in the first doped region between the well regions. | 09-18-2014 |
20140332886 | SINGLE POLY PLATE LOW ON RESISTANCE EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR DEVICE - A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The device is also characterized by conductive layer separated from a substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer. A method of fabricating a semiconductor device, in particular an ED-NMOS device, having a doped shallow drain implant of a drift region is also provided. A method is also provided for fabricating conductive layer disposed in part across a thin oxide layer and in another part across a thick/thin oxide layer. | 11-13-2014 |
20150035587 | SEMICONDUCTOR DEVICE AND OPERATING METHOD FOR THE SAME - A semiconductor device and an operating method for the same are provided. The semiconductor device includes a first doped region, a second doped region, a first doped contact, a second doped contact, a first doped layer, a third doped contact and a first gate structure. The first doped contact and the second doped contact are on the first doped region. The first doped contact and the second doped contact has a first PN junction therebetween. The first doped layer is under the first or second doped contact. The first doped layer and the first or second doped contact has a second PN junction therebetween. The second PN junction is adjoined with the first PN junction. | 02-05-2015 |
20150048415 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first doping region, a first well, a resistor element, and a first, a second, and a third heavily doping regions. The first well and the third heavily doping region are disposed in the first doping region, which is disposed on the substrate. The first heavily doping region and the second heavily doping region, which are separated from each other, are disposed in the first well. The second and the third heavily doping regions are electrically connected via the resistor element. Each of the substrate, the first well, and the second heavily doping region has a first type doping. Each of the first doping region, the first heavily doping region, and the third heavily doping region has a second type doping, complementary to the first type doping. | 02-19-2015 |
20150048451 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device and a manufacturing method for the same are provided. The semiconductor substrate includes a gate structure, a first doped contact region, a second doped contact region and a well doped region. The gate structure is on the semiconductor substrate, and has a first gate sidewall and a second gate sidewall opposite to the first gate sidewall. The first doped contact region has a first type conductivity and is formed in the semiconductor substrate on the first gate sidewall of the gate structure. The second doped contact region has the first type conductivity and is formed in the semiconductor substrate on the second gate sidewall of the gate structure. The well doped region has the first type conductivity and is under the first doped contact region. | 02-19-2015 |
20150140764 | SINGLE POLY PLATE LOW ON RESISTANCE EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR DEVICE - A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The device is also characterized by conductive layer separated from a substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer. A method of fabricating a semiconductor device, in particular an ED-NMOS device, having a doped shallow drain implant of a drift region is also provided. A method is also provided for fabricating conductive layer disposed in part across a thin oxide layer and in another part across a thick/thin oxide layer. | 05-21-2015 |
20150179754 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions. | 06-25-2015 |
20150325570 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A high voltage semiconductor device is provided, comprising a high voltage metal-oxide-semiconductor transistor (HVMOS), and a normally-on low voltage metal-oxide-semiconductor transistor (LVMOS) electrically connected to the HVMOS. The HVMOS has a first collector and a first emitter, and the LVMOS has a second collector and a second emitter, wherein the second collector of the LVMOS is electrically connected to the first emitter of the HVMOS. The LVMOS electrically connected to the HVMOS provides an electro-static discharge bipolar transistor (ESD BJT), such as a NPN-type ESD BJT. | 11-12-2015 |
20150333052 | SEMICONDUCTOR STRUCTURE AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - A semiconductor structure and an electrostatic discharge protection circuit are disclosed. The semiconductor structure includes a device structure comprising a first well region, a second well region, a source, a drain, an extending doped region, and a gate structure. The second well region has conductivity type opposite to a conductivity type of the first well region. The drain has a conductivity type same as a conductivity type of the source. The source and the drain are formed in the first well region and the second well region respectively. The extending doped region is adjoined with drain and extended under the drain. The extending doped region has a conductivity type same as the conductivity type of the drain. The gate structure is on the first well region. | 11-19-2015 |
20150372134 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure comprises a substrate, a first well formed in the substrate, a first heavily doped region formed in the first well, a second heavily doped region formed in the substrate and separated apart from the first well, a second well formed in the substrate and under the second heavily doped region, a gate dielectric formed on the substrate between the first heavily doped region and the second heavily doped region, and a gate electrode formed on the gate dielectric. The gate dielectric has a substantially uniform thickness across at least a portion extending from a side close to the second heavily doped region. The first well has a first type of doping. The first heavily doped region, the second heavily doped region and the second well have a second type of doping. | 12-24-2015 |
20150372152 | Semiconductor Device - A semiconductor device includes a substrate having a first conductivity type, a first heavily-doped region formed in the substrate and having the first conductivity type, a second heavily-doped region formed in the substrate and having the first conductivity type, and an embedded layer formed in the substrate and separated from the first and second heavily-doped regions. The embedded layer has a second conductivity type different from the first conductivity type. A portion of the embedded layer is beneath the first heavily-doped region. A third heavily-doped region is formed in the substrate, between the first and second heavily-doped regions, and contacting the embedded layer, and has the second conductivity type. | 12-24-2015 |
20160027773 | SEMICONDUCTOR DEVICE - A semiconductor device includes high-voltage (HV) and low-voltage (LV) MOS's formed in a substrate. The HV MOS includes a first semiconductor region having a first-type conductivity and a first doping level, a second semiconductor region having the first-type conductivity and a second doping level lower than the first doping level, a third semiconductor region having a second-type conductivity, and a fourth semiconductor region having the first-type conductivity. The first, second, third, and fourth semiconductor regions are arranged along a first direction, and are drain, drift, channel, and source regions, respectively, of the HV MOS. The LV MOS includes the fourth semiconductor region, a fifth semiconductor region having the second-type conductivity, and a sixth semiconductor region having the first-type conductivity. The fourth, fifth, and sixth semiconductor regions are arranged along a second direction different from the first direction, and are drain, channel, and source regions, respectively, of the LV MOS. | 01-28-2016 |
20160071963 | HIGH VOLTAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A high voltage (HV) device and method for manufacturing the same are provided, at least comprising a substrate, an insulation formed on the substrate, a deep well formed in the insulation, an air layer formed in the insulation and disposed adjacent to the bottom surface of the deep well. A bottom surface of the deep well is spaced apart from the substrate. Also, the air layer, interposed between the deep well and the substrate, is spaced apart from the substrate. In one embodiment, an air layer further communicates with an atmosphere outside the HV device, which facilitates heat dissipation. | 03-10-2016 |
20160079346 | SEMICONDUCTOR STRUCTURE - A semiconductor structure comprising an improved ESD protection device is provided. The semiconductor structure comprises a substrate, a well formed in the substrate, a first heavily doped region formed in the well, a second heavily doped region formed in the well and separated apart from the first heavily doped region, a gate structure formed on the substrate between the first heavily doped region and the second heavily doped region, a field region formed in the well under the first heavily doped region and the gate structure, and a field oxide/shallow trench isolation structure formed adjacent to the first heavily doped region. The field region is not formed under the second heavily doped region. The well and the field region have a first type of doping. The first heavily doped region and the second heavily doped region have a second type of doping. | 03-17-2016 |