Patent application number | Description | Published |
20090167338 | TEST PATTERN FOR ANALYZING CAPACITANCE OF INTERCONNECTION LINE - Disclosed is a test pattern for analyzing capacitances of interconnection lines that accounts for parasitic capacitance components. The test pattern includes a first metal line having a comb-type structure including a plurality of tines, a second metal line having a comb-type structure including a plurality of tines engaged with the tines of the first metal line, a first probe pad switchably connected to the first metal line, and a second probe pad switchably connected to the second metal line. Switchable connections between the first metal line and the first probe pad and between the second metal line and the second probe pad may be provided by first and second switch terminals, respectively. The test pattern enables a capacitance measurement that accounts for parasitic capacitance components of pads and portions of interconnection lines leading from the pads, which otherwise interfere with accurate measurement of capacitances of the interconnection lines. | 07-02-2009 |
20090168294 | CAPACITOR - A capacitor according to an embodiment can include a first dielectric layer; a first metal layer disposed below the first dielectric layer; a second dielectric layer disposed below the first metal layer; a second metal layer disposed below the second dielectric layer; a third dielectric layer disposed below the second metal layer; and a third metal layer disposed below the third dielectric layer and electrically connected to the first metal layer. | 07-02-2009 |
20100163981 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: an active region defined by a device isolation layer on and/or over a substrate; a second conductive well on and/or over the active region; an extended drain formed at one side of the second conductive well; a gate electrode on and/or over the second conductive well and the extended drain; and a source and a drain formed at both sides of the gate electrode, in which extended regions are formed at the corners of the second conductive well under the gate electrode. | 07-01-2010 |
20100164532 | APPARATUS AND METHOD FOR MEASURING CHARACTERISTICS OF SEMICONDUCTOR DEVICE - An apparatus and method for measuring the characteristics of a semiconductor device is disclosed. The measuring apparatus may include first to M-th (wherein M is a positive integer not less than 1) starved devices each being biased in response to a bias voltage varying in accordance with a variable first supply voltage, thereby varying an amount of current flowing through a semiconductor device included in the starved device. Interconnect lines may interconnect the first to M-th starved devices. A measuring unit measures at least one of a delay time caused by the semiconductor devices of the starved devices themselves, and a compound delay time caused by the semiconductor devices of the starved devices themselves plus a delay time caused by the interconnect lines. The measured results can be analyzed under conditions more approximate to diverse situations exhibited in practical chips in accordance with development of manufacturing processes and techniques. It is also possible to provide the basis of a model which more effectively represents coupling geometry of more complex semiconductor devices and interconnect lines. The basis of the model may be applied to development of various tools, etc. | 07-01-2010 |
20100169058 | MODELING STRUCTURE FOR SIMULATION OF TRAPEZOIDAL METAL LINE - Embodiments relate to a semiconductor technology, and more particularly, to a modeling structure for simulation of a trapezoidal metal line. The modeling structure for simulation of a trapezoidal metal line includes a top step with a width A, a bottom step with a width B, a middle step with a width equal to an average of the width A and the width B, and a total height C, wherein the middle step has a height equal to a value obtainable by subtracting both a height of the top step and a height of the bottom step from the total height C. | 07-01-2010 |
Patent application number | Description | Published |
20090094299 | Apparatus and method for defragmenting files on a hydrid hard disk - An apparatus and method for defragmenting files on a hybrid hard disk are provided. The apparatus includes a nonvolatile memory located within the hybrid hard disk, a loading unit reading data of a fragmented cluster and temporarily storing the read data in the nonvolatile memory, and a writing unit writing the temporarily stored data in contiguous clusters. | 04-09-2009 |
20100006031 | GAS DISTRIBUTION PLATE AND SUBSTRATE TREATING APPARATUS INCLUDING THE SAME - A gas distribution plate that is installed in a chamber providing a reaction space and supplies a reaction gas onto a substrate placed on a substrate placing plate, wherein the gas distribution plate includes: first and second surfaces opposing to each other, wherein the second surface faces the substrate placing plate and has a recess shape; and a plurality of injection holes each including: an inflow portion that extends from the first surface toward the second surface; a diffusing portion that extends from the second surface toward the first surface; and an orifice portion between the inflow portion and the diffusing portion, wherein the plurality of inflow portions of the plurality of injection holes decrease in gas path from edge to middle of the gas distribution plate, and wherein the plurality of diffusing portions of the plurality of injection holes have substantially the same gas path. | 01-14-2010 |
20150021658 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an emitter electrode and a first field plate disposed on one surface of a substrate and spaced apart from each other, a collector electrode disposed on the other surface of the substrate, a trench gate disposed in the substrate, a field diffusion junction disposed in the substrate, and a first contact connecting the trench gate and the first field plate. The first field plate has a first part extending toward the emitter electrode with respect to the first contact and having a first width, and a second part extending toward the field diffusion junction with respect to the first contact and having a second width. The second width is greater than the first width. | 01-22-2015 |
20150087360 | APPARATUS AND METHOD FOR PROCESSING VOICE COMMUNICATION IN MOBILE TERMINAL - A device and method process voice communication service. A mobile terminal device of the present disclosure includes a microphone arranged at one end of a body of the device; a speaker arranged close to the microphone; a transceiver arranged at the other end of the body; a codec including a coder connected to the microphone, a decoder connected to the speaker, and a switch of which one node is connected to one of the coder and the decoder selectively and the other node is connected to the transceiver; and a communication controller which controls the switch to establish a path between the coder and the transceiver and enables the speaker in speakerphone mode. | 03-26-2015 |
Patent application number | Description | Published |
20110319456 | BENZOARYLUREIDO COMPOUNDS, AND COMPOSITION FOR PREVENTION OR TREATMENT OF NEURODEGENERATIVE BRAIN DISEASE CONTAINING THE SAME - Novel benzoarylureido compounds and a use thereof for prevention and/or treatment of the neurodegenerative brain disease are provided. The neurodegenerative brain diseases may include Alzheimer's disease, dementia, Parkinson's disease, stroke, amyloidosis, Pick's disease, Lou Gehrig's disease, Huntington's disease, Creutzfeld-Jakob disease, and the like. | 12-29-2011 |
20140021551 | SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME - Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes active portions defined in a semiconductor substrate, a device isolation pattern in a trench formed between the active portions, a gate electrode in a gate recess region crossing the active portions and the device isolation pattern, a gate dielectric layer between the gate electrode and an inner surface of the gate recess region, and a first ohmic pattern and a second ohmic pattern on each of the active portions at both sides of the gate electrode, respectively. The first and second ohmic patterns include a metal-semiconductor compound, and a top surface of the device isolation pattern at both sides of the gate recess region is recessed to be lower than a level of a top surface of the semiconductor substrate. | 01-23-2014 |
Patent application number | Description | Published |
20140042530 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate including a first region and a second region, a trench-gate transistor in the first region, the trench-gate transistor including a first trench in the substrate, a gate filling at least part of the first trench, and a source in the substrate and on each sidewall of the first trench, a first field diffusion junction in the second region, an interlayer insulating film on the substrate, the interlayer insulating film covering the trench-gate transistor and the first field diffusion junction, a first contact in the first region, the first contact passing through the interlayer insulating film and contacting the source, and a second contact in the second region, the second contact passing through the interlayer insulating film and contacting the first field diffusion junction, the first contact and the second contact having an equal height and including a same material. | 02-13-2014 |
20140042531 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a trench in a substrate, a gate filling a part of the trench, a tilted source on a side wall of the trench, the tilted source partially overlapping the gate, an interlayer insulating film on the substrate and filling the trench, and a contact hole penetrating parts of the interlayer insulating film and the substrate and contacting the tilted source, the contact hole having a tilted surface at an angle that is equal to or larger than 80 degrees and smaller than 90 degrees. | 02-13-2014 |
20140252368 | HIGH-ELECTRON-MOBILITY TRANSISTOR - A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern. | 09-11-2014 |
20140252369 | NITRIDE-BASED SEMICONDUCTOR DEVICE - A nitride-based semiconductor device including a substrate; a GaN-containing layer on the substrate; a nitride-containing layer on the GaN layer; a channel blocking layer on the nitride-containing layer, the channel blocking layer including a nitride-based semiconductor; a gate insulation layer on the channel blocking layer; and a gate electrode on the gate insulation layer. | 09-11-2014 |
20140253241 | HIGH ELECTRON MOBILITY TRANSISTOR DEVICE - A high electron mobility transistor (HEMT) device includes a buffer layer on a substrate; a face-inversion layer on a part of the buffer layer; a plurality of semiconductor layers on the face-inversion layer and on the buffer layer; and a source electrode, a drain electrode, and a gate electrode on the plurality of semiconductor layers. The HMT device has a stable, normally Off characteristic. | 09-11-2014 |
20140291758 | SEMICONDUCTOR DEVICE HAVING PLANAR SOURCE ELECTRODE - A semiconductor device includes a channel layer on a substrate; cell trench patterns in the channel layer; and a source pattern on the cell trench patterns. The source pattern includes: grooves, each having inclined sidewalls and bottom that extends in a horizontal direction in a portion of the channel layer between the cell trench patterns, source regions at the inclined sidewalls of the grooves, source isolation regions at the bottoms of the grooves, and a source electrode at interior regions of the grooves and that has a planar upper surface. | 10-02-2014 |
20150021616 | NITRIDE-BASED SEMICONDUCTOR DEVICES - A nitride-based semiconductor device includes a barrier structure on a substrate, a nitride semiconductor layer on the barrier structure, and a source electrode, a drain electrode, and a gate electrode on the nitride semiconductor layer to be separated from each other. The barrier structure includes a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity on the first semiconductor layer, a third semiconductor layer having the first conductivity on the second semiconductor layer, and a fourth semiconductor layer having the second conductivity on the third semiconductor layer. A two-dimensional electrode gas (2DEG) channel is formed in the nitride semiconductor layer. | 01-22-2015 |
20150044854 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes preparing a substrate in which a scribe lane region and a chip region are defined, forming a trench in the scribe lane region of the substrate, forming a stopper layer in a part in the trench, and forming an alignment mark material on the stopper layer. | 02-12-2015 |