Patent application number | Description | Published |
20090195280 | INTEGRATED CIRCUIT HAVING A MEMORY WITH A PLURALITY OF STORAGE CELLS OF SYNCHRONOUS DESIGN AND CONNECTED TO CLOCK GATING UNITS - In a memory area having portions of predictable access frequency, such as in a memory area of a real time clock unit, a synchronous design may be implemented by associating storage cells of identical access frequency with a clock gating mechanism, thereby reducing power consumption. Hence, the synchronous design of the real time clock unit may provide reduced implementation effort and enhanced verification capability. | 08-06-2009 |
20090197377 | ESD POWER CLAMP WITH STABLE POWER START UP FUNCTION - A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps. | 08-06-2009 |
20090243663 | ANALOG COMPARATOR COMPRISING A DIGITAL OFFSET COMPENSATION - A digital compensation of an input stage of a comparator may be achieved by providing switched load elements, which may be appropriately connected to the differential input pair of the comparator in order to match transistor characteristics of the input pair and also match the load value of the input stage. Thus, enhanced offset behavior may be accomplished without providing an external signal and/or without requiring complex reference voltages/currents. | 10-01-2009 |
20090273053 | SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUITRY HAVING A PLURALITY OF DEVICES OF REDUCED MISMATCH - In an analog circuit portion, a systematic mismatch between a plurality of circuit elements may be reduced in view of a technology gradient by appropriately positioning the unit devices of the circuit elements so as to obtain a similar response of the circuit elements with respect to the gradient. For example, the spatial relationship of adjacent unit devices belonging to the same circuit element along an arbitrary lateral direction may be the same as the spatial relationship of adjacent unit devices of another circuit element. | 11-05-2009 |
20130027139 | RING OSCILLATOR BASED VOLTAGE CONTROL OSCILLATOR HAVING LOW-JITTER AND WIDE BANDWIDTH - The embodiments described herein provide a voltage controlled oscillator (VCO). The VCO may include, but is not limited to a voltage-to-current converter configured to receive a control voltage and to convert the control voltage to a current, a current bias circuit coupled to the voltage-to-current converter and configured to receive frequency band select digital inputs and to bias the current generated by the voltage-to-current converter based upon the band select inputs, and a ring oscillator coupled to receive the biased current and to output an oscillating signal based upon the biased current. | 01-31-2013 |
Patent application number | Description | Published |
20120300975 | SYSTEM AND METHOD FOR DETECTING THE WATERMARK USING DECISION FUSION - The present application provides a robust system and method for detecting the watermark in an electronic media, wherein the electronic media had gone through various kinds of attacks and their combinations thereof which may not be known while detecting the watermarks. The watermark detection system and method can be trained to detect or reject a particular pattern. The watermark detection system and method are based on correlation and are useful in any kind of digital watermarking applications. The watermark detection system and method perform well even when the amount of distortion is not precisely known, wherein the disclosure provides a set of templates or correlation filters, being designed for detection of watermark to cover any kind and combination of attacks. For synchronous attacks, the correlation filter designing is carried out dynamically. Particularly, the template i.e. correlation filter is an attack adaptive frequency domain pattern for watermark detection. | 11-29-2012 |
20130077787 | SYSTEM AND METHOD FOR CALL ROUTING FOR EFFICIENT USE OF TELECOMMUNICATION SPECTRUM - The present invention relates to a system and method for routing a data from one or more mobile communication channel to one or more fixed communication channel in a resource efficient manner. The delinking router of the system communicates with the one or more mobile communication channel and with one or more fixed communication channel and transmits the request to a Base Transmitting Station (BTS) for routing the data from the mobile communication channel to the fixed communication channel. The delinking router also reduces energy and spectrum consumption of the mobile communication channel by turning off its radio frequency module after routing its data to the fixed communication channel. | 03-28-2013 |
20140005815 | Method and System for Blind Audio Watermarking | 01-02-2014 |
20140198888 | DISCRETE SIGNAL SYNCHRONIZATION BASED ON A KNOWN BIT PATTERN - Systems and methods for discrete signal synchronization based on a known bit pattern are described. In one aspect of the present subject matter, a discrete signal synchronization system is configured to synchronize a preprocessed discrete signal with a modified discrete signal. The system comprises a processor and a synchronization module coupled to the processor. The synchronization module comprises an extraction module and comparison module. The extraction module determines a bit pattern from the modified discrete signal using Discrete Wavelet Transformation (DWT) and Singular Value Decomposition (SVD). The comparison module compares the determined bit pattern with a known bit pattern of the preprocessed discrete signal and records a time point at which the determined bit pattern matches with the known bit pattern of the preprocessed discrete signal as a synchronization point. | 07-17-2014 |