Patent application number | Description | Published |
20080315919 | LOGIC STATE CATCHING CIRCUITS - A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element. | 12-25-2008 |
20090040801 | Content Addressable Memory - A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance. | 02-12-2009 |
20100023684 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A CONTENT ADDRESSABLE MEMORY - Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration circuitry is configured to prevent at least one of the match lines from being restored to a pre-evaluation state responsive to corresponding enable information. | 01-28-2010 |
20100148839 | Self-Tuning Of Signal Path Delay In Circuit Employing Multiple Voltage Domains - Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation. | 06-17-2010 |
20100182823 | Low Leakage High Performance Static Random Access Memory Cell Using Dual-Technology Transistors - A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide. | 07-22-2010 |
20110140752 | Adaptive Clock Generators, Systems, and Methods - Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s). | 06-16-2011 |
20110211386 | Low Leakage High Performance Static Random Access Memory Cell Using Dual-Technology Transistors - A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide. | 09-01-2011 |
20110227639 | Method and Apparatus for Suppressing Bitline Coupling Through Miller Capacitance to a Sense Amplifier Interstitial Node - A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs. | 09-22-2011 |
20110249518 | Circuits, Systems, and Methods for Dynamic Voltage Level Shifting - Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input. | 10-13-2011 |
20130182514 | Mimicking Multi-Voltage Domain Wordline Decoding Logic for a Memory Array - Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal. | 07-18-2013 |
20130257498 | Pulse Clock Generation Logic with Built-in Level Shifter and Programmable Rising Edge and Pulse Width - Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation. | 10-03-2013 |
Patent application number | Description | Published |
20150223173 | DEGREES OF FREEDOM IN MULTICELL WIRELESS SYSTEMS WITH FULL-DUPLEX BASE STATIONS USING INTERFERENCE ALIGNMENT AND METHODS FOR ENABLING FULL-DUPLEX WITH HALF DUPLEX CLIENTS - An interference alignment system for communication structures that includes a single cell channel comprising an access point node, and a full bipartite interference channel (FBIC) configuration of a plurality of receiving nodes and a plurality of transmitting nodes. Each receiving node sees an interfering signal from all transmitting nodes. The access point node of the single cell channel provides a single node having downlink channels to all receiving nodes in the FBIC, and all of the uplink channels from the FBIC are to the single access point node to the single cell channel. | 08-06-2015 |
20150365142 | EFFICIENT LARGE-SCALE MULTIPLE INPUT MULTIPLE OUTPUT COMMUNICATIONS - Methods and systems for beam forming include measuring channel state information for a set of different codebook entries. An angle of arrival (AoA) distribution is determined with a processor using compressive testing based on the measured channel state information. A set of phase shift values is determined based on the determined AoA to perform phased array beamforming. | 12-17-2015 |
20150365143 | EFFICIENT LARGE-SCALE MULTIPLE INPUT MULTIPLE OUTPUT COMMUNICATIONS - Methods and systems for beam forming, implemented in a base station used in a communication system, include measuring channel state information (CSI) for a number of active phased-array antennas less than a full number of phased-array antennas. Analog beam forming weights are determined using the measured CSI. An optimal digital precoder is determined from the analog beam forming weights. The analog beam forming weights and optimal digital precoder are applied to one phased-array antenna. | 12-17-2015 |
20150381248 | INTERFERENCE CANCELLATION - A method implemented in an access point (AP) having N antennas used in a wireless communications system including two first client devices each of which has M antennas and two second client devices each of which has N antennas, where M and N are even is disclosed. The method comprises: performing interference alignment (IA) in common vector spaces; and delivering M+N streams. Other methods, systems, and apparatuses also are disclosed. | 12-31-2015 |
20150381334 | INTERFERENCE CANCELLATION - A method implemented in a wireless communications system including a first uplink (UL) client device, a second UL client device, a first downlink (DL) client device, and an access point (AP) is disclosed. The method comprises the following steps in this order: a) determining interference alignment (IA) solution between the first and second UL client devices and the first device; and b) determining, according to the IA solution, receive filter U | 12-31-2015 |
20150381335 | INTERFERENCE CANCELLATION - A method implemented in an access point (AP) used in a wireless communications system including a first uplink (UL) client device, a second UL client device, and a first downlink (DL) client device is disclosed. The method comprises: receiving, from the first DL client device, first composite channel matrix M | 12-31-2015 |
Patent application number | Description | Published |
20120026636 | ACTIVE AC INRUSH CURRENT CONTROL - Active inrush current control includes activating a load, the activating causing inrush current to flow, switching a semiconductor switching device to a current limiting state in response to the inrush current flow, the current limiting state being one of at least three states of the semiconductor switching device and the current limiting state dissipating the inrush current, and switching the semiconductor device to a full current flow state in response to the dissipating, the full current flow state not inhibiting current flow. | 02-02-2012 |
20120043921 | CONTROL OF POLE-CHANGE INDUCTION MOTORS - A ram air fan control system includes a ram air fan motor, the ram air fan motor being a pole-change induction motor with at least two pole-count configurations, a ram air fan contactor in operative communication with a first pole-count configuration of the ram air fan motor over a ram air fan conductor bus, a ram air fan power controller in operative communication with the ram air fan contactor, a common contactor in operative communication a second pole-count configuration of the ram air fan motor over a common conductor bus, the common conductor bus being separate and electrically isolated from the ram air fan conductor bus, and a common power controller in operative communication with the common contactor. | 02-23-2012 |
20120182656 | ACTIVE TRANSIENT CURRENT CONTROL IN ELECTRONIC CIRCUIT BREAKERS - A system and method for operating a semi-conductor based circuit breaker as a transient current limiter includes a semi-conductor switch that operates in a linear mode during a transient event and thereby reduces the transient current passing through the switch. | 07-19-2012 |
20130278229 | THERMAL STRESS REDUCTION IN AIRCRAFT MOTOR CONTROLLERS - A thermal stress reduction method includes ramping an electric power generator to start an aircraft engine, for a time period associated with the aircraft engine start sequence toggling a three-level inverter switch array to a three-level pulse width modulation mode, determining if a first time interval in the three-level pulse width modulation mode exceeded a predetermined three-level pulse width modulation mode interval, in response to the first time interval exceeding the three-level pulse width modulation mode interval, toggling the three-level inverter switch array to a two-level pulse width modulation mode, determining if a second time interval in the two-level pulse width modulation mode exceeded a predetermined two-level pulse width modulation mode interval and in response to the second time interval exceeding the two-level pulse width modulation mode interval, toggling the three-level inverter switch array to the three-level pulse width modulation mode. | 10-24-2013 |
20140250910 | THERMAL STRESS REDUCTION IN AIRCRAFT MOTOR CONTROLLERS - A thermal stress reduction method includes ramping an electric power generator to start an aircraft engine, for a time period associated with the aircraft engine start sequence toggling a three-level inverter switch array to a three-level pulse width modulation mode, determining if a first time interval in the three-level pulse width modulation mode exceeded a predetermined three-level pulse width modulation mode interval, in response to the first time interval exceeding the three-level pulse width modulation mode interval, toggling the three-level inverter switch array to a two-level pulse width modulation mode, determining if a second time interval in the two-level pulse width modulation mode exceeded a predetermined two-level pulse width modulation mode interval and in response to the second time interval exceeding the two-level pulse width modulation mode interval, toggling the three-level inverter switch array to the three-level pulse width modulation mode. | 09-11-2014 |
20140253005 | THERMAL STRESS REDUCTION IN AIRCRAFT MOTOR CONTROLLERS - A thermal stress reduction method includes ramping an electric power generator to start an aircraft engine, for a time period associated with the aircraft engine start sequence toggling a three-level inverter switch array to a three-level pulse width modulation mode, determining if a first time interval in the three-level pulse width modulation mode exceeded a predetermined three-level pulse width modulation mode interval, in response to the first time interval exceeding the three-level pulse width modulation mode interval, toggling the three-level inverter switch array to a two-level pulse width modulation mode, determining if a second time interval in the two-level pulse width modulation mode exceeded a predetermined two-level pulse width modulation mode interval and in response to the second time interval exceeding the two-level pulse width modulation mode interval, toggling the three-level inverter switch array to the three-level pulse width modulation mode. | 09-11-2014 |
Patent application number | Description | Published |
20100156196 | ELECTRICALLY CONDUCTIVE ELEMENT, SYSTEM, AND METHOD OF MANUFACTURING - An electrically conductive element, including an insulator and a first conductor, is provided, which can be affixed to a second conductor consisting of conductive structural element, wherein the insulator is positioned between the first and second conductors to electrically isolate them. A power supply may be connected between the first and second conductors to provide power thereto, and an electrical device may be connected across the first and second conductors. | 06-24-2010 |
20100170616 | ELECTRICALLY CONDUCTIVE TAPE FOR WALLS AND CEILINGS - An electrically conductive tape for walls and ceilings is provided. The tape includes a substrate configured to be applied to at least one surface including at least one surface of a wall or ceiling and at least one conductive layer applied to the substrate. The conductive layer is penetrable by at least a conductor of an electrical device to provide an electrical connection thereto. In one embodiment the conductive layer is formed from a conductive composition including an electrically conductive material therein. The conductive composition can include a conductive ink. A method of manufacturing an electrically conductive tape or film for walls and ceilings is also provided. The method includes providing a conductive composition including an electrically conductive material therein, and providing a substrate configured to be applied to at least one surface including at least one surface of a wall or ceiling. The method also includes applying the conductive composition to the substrate forming a conductive layer attached to the substrate, the conductive layer being penetrable by a conductor of an electrical device. | 07-08-2010 |
20100170702 | ELECTRICALLY CONDUCTIVE MODULE - An electrically conductive module is provided. The module includes a panel configured to engage with one or more conductive structural elements. The module further includes conductive layers formed on or in the panel. Each conductive layer has a terminal configured to be in electrical communication with at least one of the conductive structural elements. In one embodiment of the present invention, a first terminal is configured to be in electrical communication with a first conductive structural element and a second terminal is configured to be in electrical communication with a second conductive structural element. In another embodiment of the present invention, both a first terminal and a second terminal are configured to be in electrical communication with a first conductive structural element. In this embodiment, the first and second terminals are respectively configured to be in electrical communication with first and second conductive portions of the first conductive structural element. | 07-08-2010 |
20110310528 | Capacitor with Three-Dimensional High Surface Area Electrode and Methods of Manufacture - A capacitor, and methods of its manufacture, having improved capacitance efficiency which results from increasing the effective area of an electrode surface are disclosed. An improved “three-dimensional” capacitor may be constructed with electrode layers having three-dimensional aspects at the point of interface with a dielectric such that portions of the electrode extend into the dielectric layer. Advantageously, embodiments of a three-dimensional capacitor drastically reduce the space footprint that is required in a circuit to accommodate the capacitor, when compared to current capacitor designs. Increased capacitance density may be realized without using high k (high constant) dielectric materials, additional “electrode-dielectric-electrode” arrangements in an ever increasing stack, or serially stringing together multiple capacitors. | 12-22-2011 |
20120262836 | CERAMIC CAPACITOR AND METHODS OF MANUFACTURE - A capacitor includes a pair of electrodes and a metalized dielectric layer disposed between the pair of electrodes, in which the metalized dielectric layer has a plurality of metal aggregates distributed within a dielectric material. The distribution is such that a volume fraction of metal in the metalized dielectric layer is at least about 30%. Meanwhile, the plurality of metal aggregates are separated from one another by the dielectric material. A method for forming a metal-dielectric composite may include coating a plurality of dielectric particles with a metal to form a plurality of metal-coated dielectric particles and sintering the plurality of metal-coated dielectric particles at a temperature of at least about 750° C. to about 950° C. to transform the metal coatings into discrete, separated metal aggregates. Contrary to conventional techniques of separating electrodes by a dielectric tape, this inventive system and method demonstrates that a metalized dielectric layer may be formed in-situ during sintering. | 10-18-2012 |
20140233153 | METHODS FOR MANUFACTURE A CAPACITOR WITH THREE-DIMENSIONAL HIGH SURFACE AREA ELECTRODES - A capacitor, and methods of its manufacture, having improved capacitance efficiency which results from increasing the effective area of an electrode surface are disclosed. An improved “three-dimensional” capacitor may be constructed with electrode layers having three-dimensional aspects at the point of interface with a dielectric such that portions of the electrode extend into the dielectric layer. Advantageously, embodiments of a three-dimensional capacitor drastically reduce the space footprint that is required in a circuit to accommodate the capacitor, when compared to current capacitor designs. Increased capacitance density may be realized without using high k (high constant) dielectric materials, additional “electrode—dielectric—electrode” arrangements in an ever increasing stack, or serially stringing together multiple capacitors. | 08-21-2014 |
20160079023 | ELECTRICALLY CONDUCTIVE ELEMENT, SYSTEM, AND METHOD OF MANUFACTURING - An electrically conductive element, including an insulator and a first conductor, is provided, which can be affixed to a second conductor consisting of conductive structural element, wherein the insulator is positioned between the first and second conductors to electrically isolate them. A power supply may be connected between the first and second conductors to provide power thereto, and an electrical device may be connected across the first and second conductors. | 03-17-2016 |
Patent application number | Description | Published |
20110316567 | Lattice Structure for Capacitance Sensing Electrodes - One embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element comprising a main trace, where the main trace intersects each of the first plurality of sensor elements to form a plurality of intersections. A unit cell may be associated with each of the intersections, and each unit cell may designate a set of locations nearest to the corresponding intersection. A contiguous section of the main trace may cross at least one of the plurality of unit cells. Within each unit cell, the second sensor element may comprise at least one primary subtrace branching away from the main trace. | 12-29-2011 |
20120044198 | SELF SHIELDING CAPACITANCE SENSING PANEL - A self-shielding capacitive sensor array may include a first plurality of sensor elements and a second plurality of sensor elements, where each of the second plurality of sensor elements intersects each of the first plurality of sensor elements, such that each of the first plurality of sensor elements may be capacitively coupled with each of the second plurality of sensor elements. The first plurality of sensor elements may be configured to shield each of the second plurality of sensor elements from a noise source. | 02-23-2012 |
20120133611 | Asymmetric Sensor Pattern - An embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element comprising a main trace that intersects each of the first plurality of sensor elements to form a plurality of intersections. A unit cell may be associated with each of the intersections, and each unit cell may designate a set of locations nearest to a corresponding intersection. A contiguous section of the main trace may cross at least one of the plurality of unit cells. The capacitive sensor array may further comprise a plurality of open zones, where each of the plurality of open zones is staggered relative to an adjacent open zone. | 05-31-2012 |
20140118241 | INPUT LOCATION CORRECTION TABLES FOR INPUT PANELS - One or more input location correction tables are used to compensate for interference introduced into input panels and generate a corrected location based on a sensed location of the input panel. The one or more input location correction tables can include a coarse table and a fine table that stores mappings of intermediate locations mapped to by the coarse table having an accuracy that fails to satisfy a threshold coordinate accuracy. Different environments in which computing device can be situated can result in different interference being introduced, and the one or more input location correction tables can be updated based on the current environment to compensate for the interference introduced in the current environment. | 05-01-2014 |
20150193050 | Lattice Structure for Capacitance Sensing Electrodes - A sensor array includes a first sensor element of a unit cell and a second sensor element of the unit cell. The unit cell includes core traces of the first sensor element, where the core traces are the widest portion of the first sensor element. The unit cell includes main traces of the second sensor element and subtraces of the second sensor element, where each main trace crosses the first sensor element at a corresponding bridge to form an intersection of the unit cell. | 07-09-2015 |
Patent application number | Description | Published |
20080244152 | Method and Apparatus for Configuring Buffers for Streaming Data Transfer - A specification of a configurable processor is generated by generating (1) specifications of first and second stream memory interfaces to be operable to access data in accordance with first and second stream descriptors, and (2) a specification of an interim data storage device (buffer) to be accessed by the first and second stream memory interfaces and to be operable to receive data from a first computational module via the first stream memory interface and to transfer data to a second computational module via the second stream memory interface. The specifications are output and may be used to configure a configurable processor. | 10-02-2008 |
20080244169 | Apparatus for Efficient Streaming Data Access on Reconfigurable Hardware and Method for Automatic Generation Thereof - A content addressable memory (CAM) is disclosed that includes a memory having a first port configured to write a 1-bit data to the memory and a second port configured to read and write N-bit data. To update the CAM, an N-bit zero data word is written to the second port at a first address A | 10-02-2008 |
20090297061 | REPLACING IMAGE INFORMATION IN A CAPTURED IMAGE - Described herein are systems and methods for expanding upon the single-distance-based background denotation to seamlessly replace unwanted image information in a captured image derived from an imaging application so as to account for a selected object's spatial orientation to maintain an image of the selected object in the captured image. | 12-03-2009 |
20130054825 | CONTENT STREAMING IN COMMUNICATION SYSTEM - A multi-media device comprising a controller configured to determining that media presented on a multimedia interface will be subject to starvation based on a rate at which a stream of data is received and a rate at which the media is presented on a multimedia interface of the device. The controller also configured to interrupt the presentation of media on the multimedia interface and to present supplemental content on the multimedia interface starvation occurs, to buffer data from the stream of data while presenting the supplemental content, and to present media on the multimedia interface based at least partly on the buffered data after presentation of the supplemental content. | 02-28-2013 |
20130058589 | METHOD AND APPARATUS FOR TRANSFORMING A NON-LINEAR LENS-DISTORTED IMAGE - A method and apparatus for image processing a lens-distorted image (e.g., a fisheye image) is provided. The method includes partitioning coordinate points in a selected output image into tiles. The output image is an undistorted rendition of a subset of the lens-distorted image. Coordinate points on a border of the tiles in the output image are selected. For each tile, coordinate points in the lens-distorted image corresponding to each selected coordinate point in the output image are calculated. In addition, for each tile, a bounding box on the lens-distorted image is selected. The bounding box includes the calculated coordinates in the lens-distorted image. The bounding boxes are expanded so that they encompass all coordinate points in the lens-distorted image that map to all coordinate points in their respective corresponding tiles. Output pixel values are generated for each tile from pixel values in their corresponding expanded bounding boxes. | 03-07-2013 |
Patent application number | Description | Published |
20090241683 | MASS AIR FLOW SENSOR ADAPTOR - Mass air flow sensing for internal combustion engines. In one aspect, a sensor adaptor for use in an internal combustion engine includes an inlet housing including an approximately 90-degree elbow and directing air within the inlet housing to the internal combustion engine in an airflow direction. A mass air flow sensor is coupled to the housing at a location after the 90-degree elbow with respect to the airflow direction and senses the air flowing within the inlet housing. | 10-01-2009 |
20120160934 | SYSTEM, METHOD, AND APPARATUS FOR DELIVERING HIGHLY ATOMIZED DIESEL EXHAUST FLUID TO AN EXHAUST AFTERTREATMENT SYSTEM - A system includes a cylindrical blend chamber having two inlets and one outlet. The outlet is fluidly coupled to a transfer line, and a nozzle is positioned downstream of the transfer line. The nozzle is fluidly coupled to an exhaust stream of an internal combustion engine. The system further includes a first inlet fluidly coupled to a diesel exhaust fluid (DEF) stream, and a second inlet fluidly coupled to an air stream. The DEF stream and the air stream intersect at a divergent angle. | 06-28-2012 |
20140245722 | SYSTEMS AND TECHNIQUES FOR HEATING UREA INJECTION SYSTEMS - A reductant delivery system is provided for delivery of reductant to an engine exhaust aftertreatment system that is heated during cold temperature conditions. A heat exchange fluid flows through a heat exchange circuit that provides a flow path from the heat source to the doser, from the doser to the reductant storage tank, and from the reductant storage tank to the heat source. A control valve controls the flow of the heat exchange fluid in the heat exchange circuit so that at least one heat exchange cycle includes a circulation period that increases the temperature of the reductant in the doser and storage tank and a termination period where circulation is stopped until reductant temperature in the doser reaches a lower limit. | 09-04-2014 |
20150027556 | Urea Injection Systems Wash Cycles - Urea injection system wash cycle methods and systems are disclosed. An exemplary wash cycle method includes operating a urea injection system to provide urea solution to a first inlet of a blending chamber, provide pressurized gas to a second inlet of the blending chamber, and output a combined flow of pressurized gas and urea solution from the blending chamber. A pressure of the combined flow at a location downstream from the first inlet and the second inlet is monitored. A wash cycle is performed based upon the monitored pressure wherein the flow of pressurized gas is turned off and urea solution is provided to the blending chamber. An exemplary system includes a controller configured to control a urea injection system to perform a wash cycle in accordance with the exemplary method. | 01-29-2015 |
20160032805 | Reintroduction of Air in Delivery System Accumulator - According to one embodiment, an apparatus for reintroducing air includes a bypass valve that reduces pressure in an accumulator that stores reductant to less than an air supply pressure of an air supply. The apparatus also includes a metering valve that fills the accumulator with air from the air supply at the air supply pressure, and a pump that pumps reductant into the accumulator. | 02-04-2016 |