Patent application number | Description | Published |
20080265419 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE FEATURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a layer of a dielectric material. A recess is provided in the layer of dielectric material. A first glue layer and a second glue layer are formed over the recess. The first glue layer comprises titanium and the second glue layer comprises tungsten nitride. The recess is filled with a material comprising tungsten. | 10-30-2008 |
20090001526 | TECHNIQUE FOR FORMING AN INTERLAYER DIELECTRIC MATERIAL OF INCREASED RELIABILITY ABOVE A STRUCTURE INCLUDING CLOSELY SPACED LINES - By removing excess material of an interlayer dielectric material deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material, such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition. | 01-01-2009 |
20090061645 | SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTORS LATERALLY ENCLOSED BY INTERLAYER DIELECTRIC MATERIAL HAVING INCREASED INTRINSIC STRESS - By appropriately treating an interlayer dielectric material above P-channel transistors, the compressive stress may be significantly enhanced, which may be accomplished by expanding the interlayer dielectric material, for instance, by providing a certain amount of oxidizable species and performing an oxidation process. | 03-05-2009 |
20090085030 | INCREASED RELIABILITY FOR A CONTACT STRUCTURE TO CONNECT AN ACTIVE REGION WITH A POLYSILICON LINE - By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria. | 04-02-2009 |
20090085145 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE FEATURE AND METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a semiconductor substrate. A layer of an electrically insulating material is formed over the semiconductor substrate. An electrically conductive feature is formed in the layer of electrically insulating material. A first layer of a semiconductor material is formed between the electrically conductive feature and the layer of electrically insulating material. | 04-02-2009 |
20090087999 | TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL - By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer. | 04-02-2009 |
20090108462 | DUAL INTEGRATION SCHEME FOR LOW RESISTANCE METAL LAYERS - By forming a metal line extending through the entire interlayer dielectric material in resistance sensitive metallization layers, enhanced uniformity of these metallization layers may be obtained. The patterning of respective via openings may be accomplished on the basis of a recess formed in a cap layer, which additionally acts as an efficient etch stop layer during the patterning of the trenches, which extend through the entire interlayer dielectric material. Consequently, for a given design width of metal lines in resistance sensitive metallization layers, a maximum cross-sectional area may be obtained for the metal line with a high degree of process uniformity irrespective of a variation of the via density. | 04-30-2009 |
20100285668 | TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL - By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer. | 11-11-2010 |
20110117723 | NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO ALIGNMENT AND FEATURE SHAPING - By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like. | 05-19-2011 |
20110210447 | CONTACT ELEMENTS OF SEMICONDUCTOR DEVICES COMPRISING A CONTINUOUS TRANSITION TO METAL LINES OF A METALLIZATION LAYER - In sophisticated semiconductor devices, contact elements in the contact level may be formed by patterning the contact openings and filling the contact openings with the metal of the first metallization layer in a common deposition sequence. To this end, in some illustrative embodiments, a sacrificial fill material may be provided in contact openings prior to depositing the dielectric material of the first metallization layer. | 09-01-2011 |
20120319285 | INTEGRATED CIRCUITS INCLUDING BARRIER POLISH STOP LAYERS AND METHODS FOR THE MANUFACTURE THEREOF - Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer dielectric (“ILD”) layer over a semiconductor device, depositing a barrier polish stop layer over the ILD layer, and patterning at least the barrier polish stop layer and the ILD layer to create a plurality of etch features therein. Copper is plated over the barrier polish stop layer and into the plurality of etch features to produce a copper overburden overlying the barrier polish stop layer and a plurality of conductive interconnect features in the ILD layer and barrier polish stop layer. The integrated circuit is polished to remove the copper overburden and expose the barrier polish stop layer. | 12-20-2012 |
20140239503 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CAPPING LAYERS BETWEEN METAL CONTACTS AND INTERCONNECTS - Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer. | 08-28-2014 |
20140349479 | METHOD INCLUDING A REMOVAL OF A HARDMASK FROM A SEMICONDUCTOR STRUCTURE AND RINSING THE SEMICONDUCTOR STRUCTURE WITH AN ALKALINE RINSE SOLUTION - A method includes providing a semiconductor structure. The semiconductor structure includes an electrically conductive feature including a first metal, a dielectric material provided over the electrically conductive feature and a hardmask. The hardmask includes a hardmask material and is provided over the dielectric material. An opening is provided in the interlayer dielectric and the hardmask. A portion of the electrically conductive feature is exposed at a bottom of the opening. The hardmask is removed. The removal of the hardmask includes exposing the semiconductor structure to an etching solution including hydrogen peroxide and a corrosion inhibitor. After the removal of the hardmask, the semiconductor structure is rinsed. Rinsing the semiconductor structure includes exposing the semiconductor structure to an alkaline rinse solution. | 11-27-2014 |